pulse_count.tan.talkback.xml

本人编写的FPGA光电编码器输入模块,没有实验,但仿真基本实现,希望有参考价值.

<!--
This XML file (created on Tue Jun 13 16:20:04 2006) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
	<host_id>000aeb14954f</host_id>
	<nic_id>000aeb14954f</nic_id>
	<cdrive_id>988e65e0</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 176</build>
	<binary_type>32</binary_type>
	<module>quartus_tan.exe</module>
	<edition>Full Version</edition>
	<compilation_end_time>Tue Jun 13 16:20:04 2006</compilation_end_time>
</tool>
<machine>
	<os>Windows 2000</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">1302</cpu_freq>
	</cpu>
	<ram units="MB">120</ram>
</machine>
<top_file>D:/altera/fpga+dsp/pusle_count/pulse_count</top_file>
<mep_data>
	<command_line>quartus_tan --read_settings_files=off --write_settings_files=off pulse_count -c pulse_count --timing_analysis_only</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
	<info>Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning</info>
	<info>Info: Elapsed time: 00:00:02</info>
	<info>Info: Processing ended: Tue Jun 13 16:20:03 2006</info>
	<info>Info: th for register &quot;PULSE_COUNT[1]~reg0&quot; (data pin = &quot;DIRECTION&quot;, clock pin = &quot;F4_CLK&quot;) is 0.094 ns</info>
	<info>Info: - Shortest pin to register delay is 2.991 ns</info>
</messages>
<clock_settings_summary>
	<row>
		<clock_node_name>F4_CLK</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<performance>
	<nonclk>
		<type>Worst-case tsu</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>4.448 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case tco</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>7.462 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case th</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>0.094 ns</actual>
	</nonclk>
	<clk>
		<name>F4_CLK</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>286.70 MHz ( period = 3.488 ns )</actual>
	</clk>
</performance>
<compile_id>44F646DF</compile_id>
</talkback>