pulse_count.map.talkback.xml

本人编写的FPGA光电编码器输入模块,没有实验,但仿真基本实现,希望有参考价值.

<!--
This XML file (created on Tue Jun 13 16:19:23 2006) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
	<host_id>000aeb14954f</host_id>
	<nic_id>000aeb14954f</nic_id>
	<cdrive_id>988e65e0</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 176</build>
	<binary_type>32</binary_type>
	<module>quartus_map.exe</module>
	<edition>Full Version</edition>
	<compilation_end_time>Tue Jun 13 16:19:23 2006</compilation_end_time>
</tool>
<machine>
	<os>Windows 2000</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">1302</cpu_freq>
	</cpu>
	<ram units="MB">120</ram>
</machine>
<top_file>D:/altera/fpga+dsp/pusle_count/pulse_count</top_file>
<mep_data>
	<command_line>quartus_map --read_settings_files=on --write_settings_files=off pulse_count -c pulse_count</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning (10230): Verilog HDL assignment warning at pulse_count.v(15): truncated value with size 24 to match size of target (16)</warning>
	<warning>Warning (10230): Verilog HDL assignment warning at pulse_count.v(12): truncated value with size 32 to match size of target (16)</warning>
	<warning>Warning (10230): Verilog HDL assignment warning at pulse_count.v(10): truncated value with size 32 to match size of target (16)</warning>
	<info>Info: Quartus II Analysis &amp; Synthesis was successful. 0 errors, 3 warnings</info>
	<info>Info: Elapsed time: 00:00:05</info>
	<info>Info: Processing ended: Tue Jun 13 16:19:23 2006</info>
	<info>Info: Implemented 35 device resources after synthesis - the final resource count might be different</info>
	<info>Info: Implemented 16 logic cells</info>
</messages>
<analysis___synthesis_settings>
	<row>
		<option>Device</option>
		<setting>EP2C5Q208C8</setting>
	</row>
	<row>
		<option>Top-level entity name</option>
		<setting>pulse_count</setting>
		<default_value>pulse_count</default_value>
	</row>
	<row>
		<option>Family name</option>
		<setting>Cyclone II</setting>
		<default_value>Stratix</default_value>
	</row>
	<row>
		<option>Use smart compilation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Restructure Multiplexers</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Create Debugging Nodes for IP Cores</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Preserve fewer node names</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Disable OpenCore Plus hardware evaluation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Verilog Version</option>
		<setting>Verilog_2001</setting>
		<default_value>Verilog_2001</default_value>
	</row>
	<row>
		<option>VHDL Version</option>
		<setting>VHDL93</setting>
		<default_value>VHDL93</default_value>
	</row>
	<row>
		<option>State Machine Processing</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Extract Verilog State Machines</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Extract VHDL State Machines</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Add Pass-Through Logic to Inferred RAMs</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>DSP Block Balancing</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Maximum DSP Block Usage</option>
		<setting>-1</setting>
		<default_value>-1</default_value>
	</row>
	<row>
		<option>NOT Gate Push-Back</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Power-Up Don&apos;t Care</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Remove Redundant Logic Cells</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Remove Duplicate Registers</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Ignore CARRY Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore CASCADE Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore GLOBAL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore ROW GLOBAL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore LCELL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore SOFT Buffers</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Limit AHDL Integers to 32 Bits</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Optimization Technique -- Cyclone II</option>
		<setting>Balanced</setting>
		<default_value>Balanced</default_value>
	</row>
	<row>
		<option>Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II</option>
		<setting>70</setting>
		<default_value>70</default_value>
	</row>
	<row>
		<option>Auto Carry Chains</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Open-Drain Pins</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Remove Duplicate Logic</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Perform WYSIWYG Primitive Resynthesis</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Perform gate-level register retiming</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Allow register retiming to trade off Tsu/Tco with Fmax</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto ROM Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto RAM Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Shift Register Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Clock Enable Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Allow Synchronous Control Signals</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Force Use of Synchronous Clear Signals</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Resource Sharing</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Allow Any RAM Size For Recognition</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Allow Any ROM Size For Recognition</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Allow Any Shift Register Size For Recognition</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Maximum Number of M4K Memory Blocks</option>
		<setting>-1</setting>
		<default_value>-1</default_value>
	</row>
	<row>
		<option>Ignore translate_off and translate_on Synthesis Directives</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Show Parameter Settings Tables in Synthesis Report</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Ignore Maximum Fan-Out Assignments</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Retiming Meta-Stability Register Sequence Length</option>
		<setting>2</setting>
		<default_value>2</default_value>
	</row>
	<row>
		<option>PowerPlay Power Optimization</option>
		<setting>Normal compilation</setting>
		<default_value>Normal compilation</default_value>
	</row>
	<row>
		<option>HDL message level</option>
		<setting>Level2</setting>
		<default_value>Level2</default_value>
	</row>
</analysis___synthesis_settings>
<general_register_statistics>
	<row>
		<statistic>Total registers</statistic>
		<value>16</value>
	</row>
	<row>
		<statistic>Number of registers using Synchronous Clear</statistic>
		<value>16</value>
	</row>
	<row>
		<statistic>Number of registers using Synchronous Load</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Asynchronous Clear</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Asynchronous Load</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Clock Enable</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Preset</statistic>
		<value>0</value>
	</row>
</general_register_statistics>
<compilation_summary>
	<flow_status>Successful - Tue Jun 13 16:19:23 2006</flow_status>
	<quartus_ii_version>5.1 Build 176 10/26/2005 SJ Web Edition</quartus_ii_version>
	<revision_name>pulse_count</revision_name>
	<top_level_entity_name>pulse_count</top_level_entity_name>
	<family>Cyclone II</family>
	<device>EP2C5Q208C8</device>
	<timing_models>Preliminary</timing_models>
	<met_timing_requirements>N/A</met_timing_requirements>
	<total_combinational_functions>16</total_combinational_functions>
	<total_registers>16</total_registers>
	<total_pins>19</total_pins>
	<total_virtual_pins>0</total_virtual_pins>
	<total_memory_bits>0</total_memory_bits>
	<embedded_multiplier_9_bit_elements>0</embedded_multiplier_9_bit_elements>
	<total_plls>0</total_plls>
</compilation_summary>
<compile_id>C356AEC1</compile_id>
</talkback>