📄 chip.c.bak
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{
ucTmp1 =(unsigned char)(P1val&0x00FF);
ucTmp2 =(unsigned char)((P1val>>8)&0x00FF);
WrPortE(AVG_RATE_START,NULL,ucTmp2);
WrPortE(AVG_RATE_START+1,NULL,ucTmp1);
ucTmp1 =(unsigned char)(P2val&0x00FF);
ucTmp2 =(unsigned char)((P2val>>8)&0x00FF);
WrPortE(PK_RATE_START,NULL,ucTmp2);
WrPortE(PK_RATE_START+1,NULL,ucTmp1);
}
else if((uiTmp2>P1val)&&(uiTmp2<=P2val))
{
uiTmp1=uiTmp2;
ucTmp1 =(unsigned char)(uiTmp1&0x00FF);
ucTmp2 =(unsigned char)((uiTmp1>>8)&0x00FF);
WrPortE(AVG_RATE_START,NULL,ucTmp2);
WrPortE(AVG_RATE_START+1,NULL,ucTmp1);
ucTmp1 =(unsigned char)(P2val&0x00FF);
ucTmp2 =(unsigned char)((P2val>>8)&0x00FF);
WrPortE(PK_RATE_START,NULL,ucTmp2);
WrPortE(PK_RATE_START+1,NULL,ucTmp1);
}
else
{
uiTmp1=uiTmp2;
ucTmp1 =(unsigned char)(uiTmp1&0x00FF);
ucTmp2 =(unsigned char)((uiTmp1>>8)&0x00FF);
WrPortE(AVG_RATE_START,NULL,ucTmp2);
WrPortE(AVG_RATE_START+1,NULL,ucTmp1);
uiTmp1=uiTmp2;
uiTmp1+=(uiTmp2>>1);
ucTmp1 =(unsigned char)(uiTmp1&0x00FF);
ucTmp2 =(unsigned char)((uiTmp1>>8)&0x00FF);
WrPortE(PK_RATE_START,NULL,ucTmp2);
WrPortE(PK_RATE_START+1,NULL,ucTmp1);
}
}
/*** BeginHeader SetSrcIP */
nodebug xmem void SetSrcIP(void);
/*** EndHeader */
nodebug xmem void SetSrcIP()
{
int j;
unsigned char ucTmp;
unsigned long ulTmp;
ulTmp=g_AddrInfo[UserIndx].ulIpAddr;
for(j=0;j<4;++j)
{
ucTmp=(unsigned char)(ulTmp&0x000000FF);
WrPortE((SRC_IP_ADDR_START+(3-j)),NULL,ucTmp);
ulTmp>>=8;
}
}
/*** BeginHeader CfgFpga */
nodebug xmem void CfgFpga(void);
/*** EndHeader */
nodebug xmem void CfgFpga()
{
int j;
unsigned int uiTmp1,uiTmp2;
unsigned char ucTmp1;
unsigned char ucTmp2;
unsigned char ucTmp3;
for(j=0;j<6;++j)
{
WrPortE(SRC_MAC_ADDR_START+j,NULL,g_AddrInfo[UserIndx].ucMacAddr[j]);
}
SetSrcIP( );
ucTmp1=(unsigned char)((g_AddrInfo[UserIndx].uiUDPPort>>8)&0x00FF);
ucTmp2=(unsigned char)(g_AddrInfo[UserIndx].uiUDPPort&0x00FF);
WrPortE(UDP_PORT_START,NULL,ucTmp1);
WrPortE(UDP_PORT_START+1,NULL,ucTmp2);
ucTmp1=(unsigned char)((g_AddrInfo[UserIndx].uiFrmType>>8)&0x00FF);
ucTmp2=(unsigned char)(g_AddrInfo[UserIndx].uiFrmType&0x00FF);
WrPortE(HARD_TYPE_START,NULL,ucTmp1);
WrPortE(HARD_TYPE_START+1,NULL,ucTmp2);
for(j=0;j<MAX_CHANNEL;++j)
{
WrPortE(DEPTH_CTRL_A+j,NULL,(g_AddrInfo[UserIndx].SecdE1Para[j].CacheLen<<1));
if(g_AddrInfo[UserIndx].SecdE1Para[j].CacheLen<8)
{
WrPortE(THRESH_A+j,NULL,8);
}
else if(g_AddrInfo[UserIndx].SecdE1Para[j].CacheLen<16)
{
WrPortE(THRESH_A+j,NULL,14);
}
else if(g_AddrInfo[UserIndx].SecdE1Para[j].CacheLen<32)
{
WrPortE(THRESH_A+j,NULL,28);
}
else if(g_AddrInfo[UserIndx].SecdE1Para[j].CacheLen>=32)
{
WrPortE(THRESH_A+j,NULL,40);
}
}
SetPara1();
//WrPortE(E1_Or_T1,NULL,g_AddrInfo[UserIndx].TirdE1Para.E1orT1);
SetFpgaE1OrT1();
if(g_AddrInfo[UserIndx].TirdE1Para.E1orT1==0)
{
E1Set( );
}
else
{
T1Set( );
}
///////////////////////////////////////////////////////////////////////////////////////////
SetLenCodeCnt( );
IpHead( );
WrPortE(RMT_UP,NULL,0xFF);
//reset fpga
BitWrPortI( PDDR, &PDDRShadow, 0, 3 );
Longdelay();
BitWrPortI( PDDR, &PDDRShadow, 1, 3 );
}
/*** BeginHeader SetLenCodeCnt */
void SetLenCodeCnt(void);
/*** EndHeader */
void SetLenCodeCnt(void)
{
switch(g_AddrInfo[UserIndx].TirdE1Para.EnLev&0x07)
{
case 0x01:
WrPortE(LOAD_CNT_START,NULL,0x1F);
WrPortE(LOAD_CNT_START+1,NULL,0x3F);
break;
case 0x02:
WrPortE(LOAD_CNT_START,NULL,0x3E);
WrPortE(LOAD_CNT_START+1,NULL,0x7F);
break;
case 0x03:
WrPortE(LOAD_CNT_START,NULL,0x5D);
WrPortE(LOAD_CNT_START+1,NULL,0xBF);
break;
case 0x04:
WrPortE(LOAD_CNT_START,NULL,0x7C);
WrPortE(LOAD_CNT_START+1,NULL,0xFF);
break;
case 0x05:
WrPortE(LOAD_CNT_START,NULL,0x9C);
WrPortE(LOAD_CNT_START+1,NULL,0x3F);
break;
default:
WrPortE(LOAD_CNT_START,NULL,0x1F);
WrPortE(LOAD_CNT_START+1,NULL,0x3F);
break;
}
}
/*** BeginHeader CP5009_Read */
unsigned char CP5009_Read(unsigned char spi_addr);
/*** EndHeader */
unsigned char CP5009_Read(unsigned char spi_addr)
{
unsigned char reByte,i;
reByte = 0;
for (i = 0;i<16;i++)
{
if (i == 0)
{
WrPortI(PFDR,&PFDRShadow, PFDRShadow | 0x04); //MOSI
WrPortI(PDDR,&PDDRShadow,PDDRShadow &(~0x20)); //CS
WrPortI(PFDR,&PFDRShadow, PFDRShadow & (~0x01));
WrPortI(PFDR,&PFDRShadow, PFDRShadow | 0x01); //SCLK rising_edge send
}
else if (i <= 7){
if ((spi_addr & 0x01) == 0x01)
WrPortI(PFDR,&PFDRShadow, PFDRShadow | 0x04); //MOSI
else
WrPortI(PFDR,&PFDRShadow, PFDRShadow & (~0x04));
spi_addr >>= 1;
WrPortI(PFDR,&PFDRShadow, PFDRShadow & (~0x01));
WrPortI(PFDR,&PFDRShadow, PFDRShadow | 0x01); //SCLK rising_edge send
}
else
{
WrPortI(PFDR,&PFDRShadow, PFDRShadow & (~0x01));
WrPortI(PFDR,&PFDRShadow, PFDRShadow | 0x01); //SCLK rising_edge send
reByte >>= 1;
if (BitRdPortI(PFDR,1) == 1) //MISO falling_edge rec
reByte |= 0x80;
}
}
WrPortI(PDDR,&PDDRShadow,PDDRShadow |0x20);//CS
//WrPortI(PDB5R,NULL,0xFF); //CS
return reByte;
}
/*** BeginHeader CP5009_Write */
void CP5009_Write(unsigned char spi_addr,unsigned char spi_data);
/*** EndHeader */
void CP5009_Write(unsigned char spi_addr,unsigned char spi_data)
{
unsigned char i;
for (i = 0 ;i <16;i++)
{
if (i == 0)
{
WrPortI(PFDR,&PFDRShadow, PFDRShadow & (~0x04)); //MOSI
//WrPortI(PDB5R,NULL,0x00); //CS
WrPortI(PDDR,&PDDRShadow,PDDRShadow &(~0x20));
}
else if (i <= 7)
{
if ((spi_addr & 0x01) == 0x01)
{
WrPortI(PFDR,&PFDRShadow, PFDRShadow | 0x04); //MOSI
}
else
{
WrPortI(PFDR,&PFDRShadow, PFDRShadow & (~0x04));
}
spi_addr >>= 1;
}
else
{
if ((spi_data & 0x01) == 0x01)
{
WrPortI(PFDR,&PFDRShadow, PFDRShadow | 0x04); //MOSI
}
else
{
WrPortI(PFDR,&PFDRShadow, PFDRShadow & (~0x04));
}
spi_data >>= 1;
}
WrPortI(PFDR,&PFDRShadow, PFDRShadow & (~0x01));
WrPortI(PFDR,&PFDRShadow, PFDRShadow | 0x01); //SCLK rising_edge send
}
//WrPortI(PDB5R,NULL,0xff); //CS
WrPortI(PDDR,&PDDRShadow,PDDRShadow |0x20);
}
/*** BeginHeader */
#endif
/*** EndHeader */
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