📄 chip.c
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/*** BeginHeader */
#ifndef _CHIP_FUNC_
#define _CHIP_FUNC_
#define DELAY 3
#define DISP_REMOTE_LED 5
#define TEST1_LED 4
#define TEST2_LED 7
#define DEFAULT_IP 6
#define E1_FRAME_LEN 32
#define T1_FRAME_LEN 26
////////////////////////////////////////////////////////////////////////////
#define CHAN_OFFSET (0x0040)
#define OFFSET_LEN (0x03)
/////////////////////---A----////////////////////////
#define A_CHAN_MISC (0xC000)//
#define A_DST_MAC_START (0xC001)//6 Bytes
#define A_CHAN_TOS (0xC009)//3 Bits
#define A_CHAN_IP_LEN_START (0xC00A)//2 Bytes
#define A_CHAN_TTL (0xC00C)//1 Bytes
#define A_CHAN_INI_SUM0_START (0xC010)//2 Bytes
#define A_CHAN_INI_SUM1_START (0xC012)//2 Bytes
#define A_CHAN_INI_SUM2_START (0xC014)//2 Bytes
#define A_CHAN_DST_IP_START (0xC016)//4 Bytes
#define A_CHAN_UDP_PORT_START (0xC01A)//2 Bytes
#define A_VLAN_TAG_START (0xC01C)//2 Bytes
#define A_FRAG_START (0xC01E)//2 Bytes
///////////////////////---B-----/////////////////////////
#define B_CHAN_MISC (A_CHAN_MISC + CHAN_OFFSET)//
#define B_DST_MAC_START (A_DST_MAC_START + CHAN_OFFSET)//6 Bytes
#define B_CHAN_TOS (A_CHAN_TOS + CHAN_OFFSET)//3 Bits
#define B_CHAN_IP_LEN_START (A_CHAN_IP_LEN_START + CHAN_OFFSET)//2 Bytes
#define B_CHAN_TTL (A_CHAN_TTL + CHAN_OFFSET)//1 Bytes
#define B_CHAN_INI_SUM0_START (A_CHAN_INI_SUM0_START + CHAN_OFFSET)//2 Bytes
#define B_CHAN_INI_SUM1_START (A_CHAN_INI_SUM1_START + CHAN_OFFSET)//2 Bytes
#define B_CHAN_INI_SUM2_START (A_CHAN_INI_SUM2_START + CHAN_OFFSET)//2 Bytes
#define B_CHAN_DST_IP_START (A_CHAN_DST_IP_START + CHAN_OFFSET)//4 Bytes
#define B_CHAN_UDP_PORT_START (A_CHAN_UDP_PORT_START + CHAN_OFFSET)//2 Bytes
#define B_VLAN_TAG_START (A_VLAN_TAG_START + CHAN_OFFSET)//2 Bytes
///////////////////////---C-----/////////////////////////
#define C_CHAN_MISC (B_CHAN_MISC + CHAN_OFFSET)//
#define C_DST_MAC_START (B_DST_MAC_START + CHAN_OFFSET)//6 Bytes
#define C_CHAN_TOS (B_CHAN_TOS + CHAN_OFFSET)//3 Bits
#define C_CHAN_IP_LEN_START (B_CHAN_IP_LEN_START + CHAN_OFFSET)//2 Bytes
#define C_CHAN_TTL (B_CHAN_TTL + CHAN_OFFSET)//1 Bytes
#define C_CHAN_INI_SUM0_START (B_CHAN_INI_SUM0_START + CHAN_OFFSET)//2 Bytes
#define C_CHAN_INI_SUM1_START (B_CHAN_INI_SUM1_START + CHAN_OFFSET)//2 Bytes
#define C_CHAN_INI_SUM2_START (B_CHAN_INI_SUM2_START + CHAN_OFFSET)//2 Bytes
#define C_CHAN_DST_IP_START (B_CHAN_DST_IP_START + CHAN_OFFSET)//4 Bytes
#define C_CHAN_UDP_PORT_START (B_CHAN_UDP_PORT_START + CHAN_OFFSET)//2 Bytes
#define C_VLAN_TAG_START (B_VLAN_TAG_START + CHAN_OFFSET)//2 Bytes
///////////////////////---D-----/////////////////////////
#define D_CHAN_MISC (C_CHAN_MISC + CHAN_OFFSET)//
#define D_DST_MAC_START (C_DST_MAC_START + CHAN_OFFSET)//6 Bytes
#define D_CHAN_TOS (C_CHAN_TOS + CHAN_OFFSET)//3 Bits
#define D_CHAN_IP_LEN_START (C_CHAN_IP_LEN_START + CHAN_OFFSET)//2 Bytes
#define D_CHAN_TTL (C_CHAN_TTL + CHAN_OFFSET)//1 Bytes
#define D_CHAN_INI_SUM0_START (C_CHAN_INI_SUM0_START + CHAN_OFFSET)//2 Bytes
#define D_CHAN_INI_SUM1_START (C_CHAN_INI_SUM1_START + CHAN_OFFSET)//2 Bytes
#define D_CHAN_INI_SUM2_START (C_CHAN_INI_SUM2_START + CHAN_OFFSET)//2 Bytes
#define D_CHAN_DST_IP_START (C_CHAN_DST_IP_START + CHAN_OFFSET)//4 Bytes
#define D_CHAN_UDP_PORT_START (C_CHAN_UDP_PORT_START + CHAN_OFFSET)//2 Bytes
#define D_VLAN_TAG_START (C_VLAN_TAG_START + CHAN_OFFSET)//2 Bytes
////////////////////////////////////////////////////////////////////////////
#define GAP_OFFSET (0x0020)
#define GAP_TAG_EN (0xC200)
#define GAP_TAG_START (0xC201)
#define FIRST_CLR_GAP_TAG (0xC205)
#define SECOND_CLR_GAP_TAG (0xC206)
#define FIRST_REF_DATA (0xC207)
#define SECOND_REF_DATA (0xC208)
////////////////////////////---IP/MAC----//////////////////////////////////
#define SRC_MAC_ADDR_START (0xC300)
#define SRC_IP_ADDR_START (0xC306)
#define HARD_TYPE_START (0xC30A)
#define UDP_PORT_START (0xC30C)
#define UDP_PORT_START (0xC30C)
#define AVG_RATE_START (0xC30E)
#define PK_RATE_START (0xC310)
#define IP_PROTOCOL (0xC312)
////////////////////////////----E1/T1----////////////////////////////////////
#define FPGA_VER_ID_START (0xC320)//3 byte
#define CHAN_ENABLE (0xC323)
#define CHAN_ALARM (0xC324)
#define CHAN_TMOD_LEN_CODE (0xC325)
#define LB_REG (0xC326)
#define DEPTH_CTRL_A (0xC327)
#define DEPTH_CTRL_B (0xC328)
#define DEPTH_CTRL_C (0xC329)
#define DEPTH_CTRL_D (0xC32A)
#define PACK_LOS (0xC32B)
#define PLOS_CNT_A (0xC32C)
#define PLOS_CNT_B (0xC32D)
#define PLOS_CNT_C (0xC32E)
#define PLOS_CNT_D (0xC32F)
#define FIRST_CLR_ETH_PACK (0xC330)
#define SECOND_CLR_ETH_PACK (0xC331)
#define FIRST_CLR_E1_PACK (0xC332)
#define SECOND_CLR_E1_PACK (0xC333)
#define FIRST_CLR_OK (0xC34C)
#define SECOND_CLR_OK (0xC34D)
#define REMOTE_STATUS (0xC334)
#define REMOTE_LB_STATUS (0xC335)
#define THRESH_A (0xC336)
#define E1_Or_T1 (0xC33A)
#define LOAD_CNT_START (0xC33B)
////////////////////////////////////----ARP-----////////////////////////////////
#define CTRL_ARP (0xC340)//Bit0
#define ARP_IP_ADDR_START (0xC341)//4 bytes
#define MARK_ARP_OK (0xC345)//Bit0
#define ARP_IP_OF_MAC_START (0xC346)//6 byetes
/////////////////////////////////////-----LED Control------///////////////////////
#define E1_ALARM (0xC360)
#define CPU_RUN (0xC361)
#define PKT_LOS (0xc362)
#define RMT_UP (0xc363)
///////////////////////////////////////////////////////////////////////////////////
#define FILTER (0xC364)
#define TEST_P (0xC368)
/*** EndHeader */
/*** BeginHeader InitSystem */
nodebug xmem void InitSystem(void);
/*** EndHeader */
nodebug xmem void InitSystem()
{
IniRabbit();
RstChip();
}
/*** BeginHeader IniRabbit */
nodebug xmem void IniRabbit(void);
/*** EndHeader */
nodebug xmem void IniRabbit()
{
WrPortI( PBDDR, &PBDDRShadow, 0x60 );
WrPortI( PBDR, &PBDRShadow, 0x00 );
// Set the PD data direction PD output
WrPortI( PDDDR, &PDDDRShadow, 0xFC );
WrPortI( PDDR, &PDDRShadow, 0xFF );
//WrPortI( PDDCR, &PDDCRShadow, 0xFC );
WrPortI(PFDDR,&PFDDRShadow,0xFD); //ini SPI
WrPortI( PFFR, &PFFRShadow, 0x00 );
WrPortI( PFDCR, &PFDCRShadow, 0x00 );
WrPortI( PFDR, &PFDRShadow, 0x00 );
// Set the PE
WrPortI( PEFR, &PEFRShadow, 0xff );
// Set all PE pins as outputs
WrPortI( PEDDR, &PEDDRShadow, 0xff );
// All bits outpus 1
WrPortI( PEDR, &PEDRShadow, 0xff );
WrPortI(IB6CR,NULL,0x48 ); //en PE6
TimerBInit( 20000L, 1 );
}
/*** BeginHeader RstChip */
nodebug xmem void RstChip(void);
/*** EndHeader */
nodebug xmem void RstChip()
{
BitWrPortI( PDDR, &PDDRShadow, 0, 2 );//nconfig
// Reset the FPGA
BitWrPortI( PDDR, &PDDRShadow, 0, 3 );//reset fpga
// Reset the ETH chip
BitWrPortI( PDDR, &PDDRShadow, 0, 4 );// reset 5325
Longdelay();
BitWrPortI( PDDR, &PDDRShadow, 1, 2 );
BitWrPortI( PDDR, &PDDRShadow, 1, 3 );
BitWrPortI( PDDR, &PDDRShadow, 1, 4 );
CP5009_Write(0x0a,0x01);//Init CP5009
}
/*** BeginHeader T1Set */
nodebug xmem void T1Set(void);
/*** EndHeader */
nodebug xmem void T1Set(void)
{
unsigned char i;
for (i = 0;i <8;i++)
{
CP5009_Write(0x11,0x03); // PSD
CP5009_Write(0x10,i); //PSI
}
}
/*** BeginHeader E1Set */
nodebug xmem void E1Set(void);
/*** EndHeader */
nodebug xmem void E1Set(void)
{
CP5009_Write(0x0a,0x01);
CP5009_Write(0x11,0x00);
}
/*** BeginHeader CalPval */
nodebug xmem void CalPval(void);
/*** EndHeader */
nodebug xmem void CalPval()
{
unsigned char j;
unsigned char ucTmp1;
unsigned char ucTmp2;
unsigned char Normal,Unnormal;
unsigned int uiTmp1,uiTmp2;
unsigned int P0val,P1val,P2val;
Normal=0;
Unnormal=0;
Status.Los=RdPortE(CHAN_ALARM);
for(j=0;j<MAX_CHANNEL;++j)
{
if((g_AddrInfo[UserIndx].FirE1Para[j].Enable==1)&&(g_AddrInfo[UserIndx].FirE1Para[j].EnArp==0x00))
{
switch(Status.Los&0x03)
{
case 0x00:
Unnormal+=1;
break;
case 0x01:
Normal+=1;
break;
case 0x02:
Normal+=1;
break;
default:
Unnormal+=1;
break;
}
Status.Los>>=2;
}
}
ucTmp1 = g_AddrInfo[UserIndx].TirdE1Para.EnLev&0x07;
if(g_AddrInfo[UserIndx].TirdE1Para.E1orT1==0)
{
P0val=(128+256*ucTmp1)*Normal+80*Unnormal;
}
else
{
P0val=(128+208*ucTmp1)*Normal+80*Unnormal;
}
P1val=((P0val+128)/2);
P2val=((P0val+1536)/2);
Test.Unnormal=Unnormal;
Test.Normal=Normal;
uiTmp1 = g_AddrInfo[UserIndx].TirdE1Para.Upwidth;
uiTmp1>>=4;
uiTmp1=uiTmp1*ucTmp1;
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