bcm5325.c

这是一个在在Dynamic C环境下实现的设备web服务器的建立

/*================================================================================================
		Macros for the ETH chip 5325 registers' addesses
================================================================================================*/
#define ETH_ACCREG_WAIT							5
#define ETH_ACCREG_BADCNT						1

#define B5325_PAGE_CTRL							0x00
	// x = 0~4
	#define B5325_PORT_CTRL(x)					(0x00 + (x))
#define B5325_PAGE_STAT							0x01
	// x = 0~1
	#define B5325_LINK_STAT_SUM(x)				(0x00 + (x))
	// x = 0~1
	#define B5325_LINK_STAT_CHG(x)				(B5325_LINK_STAT_SUM(2) + (x))
	// x = 0~1
	#define B5325_PORT_SPED_SUM(x)				(B5325_LINK_STAT_CHG(2) + (x))
	// x = 0~1
	#define B5325_DPLX_STAT_SUM(x)				(B5325_PORT_SPED_SUM(2) + (x))
#define B5325_PAGE_MMR							0x02
#define B5325_PAGE_MIBA							0x03
#define B5325_PAGE_ARLC							0x04
#define B5325_PAGE_ARLA							0x05
#define B5325_PAGE_MFAR							0x06
#define B5325_PAGE_GMAR							0x08
//#define B5325_PAGE_Reserve					0x07~0x0F
// x = 0~4
#define B5325_PAGE_MIIP(x)						(0x10 + (x))
	// Control register addr
	#define B5325_MII_CTRL(x)					(0x00 + (x))
//#define B5325_PAGE_Reserve					0x15~0x17
#define B5325_PAGE_MIP8							0x18
#define B5325_PAGE_GMPR							0x19
//#define B5325_PAGE_Reserve					0x1A~0x1F
// x = 0~4
#define B5325_PAGE_MIBP(x)						(0x20 + (x))
//#define B5325_PAGE_Reserve					0x25~0x27
#define B5325_PAGE_MIB8							0x28
//#define B5325_PAGE_Reserve					0x29~0x2F
#define B5325_PAGE_QOSR							0x30
#define B5325_PAGE_VLAN							0x31
//#define B5325_PAGE_Reserve					0x32~0xEF

// i = 0~7
#define B5325_S_DIO(i)							(0xF0 + (i))
//#define B5325_S_Reserve						0xF8~0xFD
#define B5325_S_STS								0xFE
	#define B5325_S_SPIF						0x80
	#define B5325_S_RACK						0x20
	#define B5325_S_TXRDY						0x02
	#define B5325_S_RXRDY						0x01
#define B5325_S_SPG								0xFF

/*================================================================================================
	START:		Functions on the ETH chip
================================================================================================*/
/*** BeginHeader EthRxBits */
unsigned char EthRxBits(void);
/*** EndHeader */
unsigned char EthRxBits(void)
{
	// The CPU reads data on the rising edge of the clock
	// Bits' order : the highest --> the lowest
	auto unsigned char			i;
	auto unsigned char			ucByte;
	auto unsigned int			uiDelay;

	ucByte	= 0;
	for( i = 0; i < 8; ++i )
	{
		ucByte		<<= 1;

		//BitWrPortI( PFDR, &PFDRShadow, 0, 0 );
		//for( uiDelay = 0; uiDelay < DELAY; ++uiDelay )
		//	;
		//BitWrPortI( PDDR, &PDDRShadow, 1, 0 );
		//for( uiDelay = 0; uiDelay < DELAY; ++uiDelay )
		//	;
		WrPortI(PFDR,&PFDRShadow, PFDRShadow & (~0x01));
		WrPortI(PFDR,&PFDRShadow, PFDRShadow | 0x01);	

		ucByte		|= (RdPortI(PFDR) & 0x02) ? 1 : 0;
	}

	//
	return ucByte;
}
/*** BeginHeader EthWxBits */
void EthWxBits( unsigned char ucData );
/*** EndHeader */
void EthWxBits( unsigned char ucData )
{
	// The chip reads data on the rising edge of the clock
	// Bits' order : the highest --> the lowest
	auto unsigned char			i;
	auto unsigned char			ucByte;
	auto unsigned int			uiDelay;

	ucByte		= ucData;
	for( i = 0; i < 8; ++i )
	{
		WrPortI(PFDR,&PFDRShadow, PFDRShadow & (~0x01));
		
		WrPortI(PFDR,&PFDRShadow, PFDRShadow | 0x01);	
		
		if( ucByte & 0x80 )
		{
			//BitWrPortI( PFDR, &PFDRShadow, 1, 2 );
			WrPortI(PFDR,&PFDRShadow, PFDRShadow | 0x04); 
		}
		else
		{
			//BitWrPortI( PFDR, &PFDRShadow, 0, 2 );
			WrPortI(PFDR,&PFDRShadow, PFDRShadow & (~0x04));
		}

		//BitWrPortI( PFDR, &PFDRShadow, 0, 0 );
		//for( uiDelay = 0; uiDelay < DELAY; ++uiDelay )
		//	;
		//BitWrPortI( PFDR, &PFDRShadow, 1, 0 );
		//for( uiDelay = 0; uiDelay < DELAY; ++uiDelay )
			;

		ucByte		<<= 1;
	}
}

/*** BeginHeader GetOffset */
unsigned char GetOffset( unsigned char ucAddr, unsigned char ucBase, unsigned char ucByteWd );
/*** EndHeader */
unsigned char GetOffset( unsigned char ucAddr, unsigned char ucBase, unsigned char ucByteWd )
{
	return ucAddr - (ucBase + ((ucAddr - ucBase)/ucByteWd)*ucByteWd);
}

/*** BeginHeader EthRead */
unsigned char EthRead( unsigned char ucPage, unsigned char ucAddr,unsigned char index );
/*** EndHeader */
unsigned char EthRead( unsigned char ucPage, unsigned char ucAddr,unsigned char index )
{
	auto int						iTimer;
	auto unsigned char				ucBadCnt;
	auto unsigned char				ucByte;
	auto unsigned char				ucRegSize;
	auto unsigned char				ucOffset;

	// Get the size of the register and the offset of the byte in the register
	ucOffset	= EthRegLen( ucPage, ucAddr, &ucRegSize );

	if( ucAddr >= B5325_S_DIO(0) )
	{
		EthByteRd( ucAddr, 1, &ucByte, index );
	}
	else
	{
		iTimer		= ETH_ACCREG_WAIT + 1;
		ucBadCnt	= 0;
		ucByte		= B5325_S_SPIF;
		// SPI_SPIF == 0?
		while(ucByte & B5325_S_SPIF)
		{
			if( iTimer > ETH_ACCREG_WAIT )
			{
				EthByteWt( B5325_S_SPG, 1, &ucPage,index );
				iTimer	= 0;
				ucBadCnt++;
				if( ucBadCnt > ETH_ACCREG_BADCNT )
					break;
			}
			else
			{
				iTimer++;
			}

			// Read the SPI_STS
			EthByteRd( B5325_S_STS, 1, &ucByte,index );
		}
		g_EthBadFlg	= (ucBadCnt > ETH_ACCREG_BADCNT) ? 1 : 0;

 		// Write the new page address
		EthByteWt( B5325_S_SPG, 1, &ucPage,index );

		// Read the address, but dicard the return value
		EthByteRd( ucAddr - ucOffset, 1, &ucByte ,index);

		iTimer	= 0;
		ucByte	= (~B5325_S_RACK) & 0xFF;
		// B5325_S_RACK == 1?
		while(!(ucByte & B5325_S_RACK))
		{
			if( iTimer > ETH_ACCREG_WAIT )
			{
				break;
			}
			else
			{
				iTimer++;
			}
			// Read the SPI_STS
			EthByteRd( B5325_S_STS, 1, &ucByte,index );
		}
		EthByteRd( B5325_S_DIO(0), ucRegSize, g_B5325Buf,index );
		ucByte	= g_B5325Buf[ucOffset];

		g_EthBadFlg	= (iTimer > ETH_ACCREG_WAIT) ? 1 : 0;
	}

	return ucByte;
}

/*** BeginHeader EthRegLen */
unsigned char EthRegLen( unsigned char ucPage, unsigned char ucAddr, unsigned char * pRegSize );
/*** EndHeader */
unsigned char EthRegLen( unsigned char ucPage, unsigned char ucAddr, unsigned char * pRegSize )
{
	auto unsigned char			ucBase;

	switch( ucPage )
	{
		case B5325_PAGE_CTRL:
			if( ucAddr >= 0x0C && ucAddr <= 0x0D )
			{
				*pRegSize	= 2;
				return GetOffset( ucAddr, 0x0C, 2 );
			}
		break;
		case B5325_PAGE_STAT:
			if( ucAddr >= 0x00 && ucAddr <= 0x0D )
			{
				*pRegSize	= 2;
				return GetOffset( ucAddr, 0x00, 2 );
			}
			else if( ucAddr >= 0x10 && ucAddr <= 0x45 )
			{
				*pRegSize	= 6;
				return GetOffset( ucAddr, 0x10, 6 );
			}
		break;
		case B5325_PAGE_MMR:
			if( 	(ucAddr >= 0x04 && ucAddr <= 0x05)
				||	(ucAddr >= 0x10 && ucAddr <= 0x15)
				||	(ucAddr >= 0x1C && ucAddr <= 0x1F) )
			{
				if( ucAddr >= 0x1C )
					ucBase	= 0x1C;
				else if(ucAddr >= 0x10)
					ucBase	= 0x10;
				else
					ucBase	= 0x04;
				*pRegSize	= 2;
				return GetOffset( ucAddr, ucBase, 2 );
			}
			else if((ucAddr >= 0x06 && ucAddr <= 0x09) )
			{
				*pRegSize	= 4;
				return GetOffset( ucAddr, 0x06, 4 );
			}
			else if((ucAddr >= 0x16 && ucAddr <= 0x1B)
				||	(ucAddr >= 0x20 && ucAddr <= 0x25) )
			{
				ucBase	= (ucAddr >= 0x20) ? 0x20 : 0x16;
				*pRegSize	= 6;
				return GetOffset( ucAddr, ucBase, 6 );
			}
		break;
		case B5325_PAGE_MIBA:
			if( 	(ucAddr >= 0x00 && ucAddr <= 0x05)
				||	(ucAddr >= 0x12 && ucAddr <= 0x13) )
			{
				ucBase	= (ucAddr >= 0x12) ? 0x12 : 0x00;
				*pRegSize	= 2;
				return GetOffset( ucAddr, ucBase, 2 );
			}
			else if((ucAddr >= 0x06 && ucAddr <= 0x11) )
			{
				*pRegSize	= 6;
				return GetOffset( ucAddr, 0x06, 6 );
			}
		break;
		case B5325_PAGE_ARLC:
			if( 	(ucAddr >= 0x16 && ucAddr <= 0x17)
				||	(ucAddr >= 0x26 && ucAddr <= 0x27)
				||	(ucAddr >= 0x30 && ucAddr <= 0x33) )
			{
				if(ucAddr >= 0x30)
					ucBase	= 0x30;
				else if(ucAddr >= 0x26)
					ucBase	= 0x26;
				else
					ucBase	= 0x16;
				*pRegSize	= 2;
				return GetOffset( ucAddr, ucBase, 2 );
			}
			else if((ucAddr >= 0x10 && ucAddr <= 0x15)
				||	(ucAddr >= 0x20 && ucAddr <= 0x25) )
			{
				ucBase	= (ucAddr >= 0x20) ? 0x20 : 0x10;
				*pRegSize	= 6;
				return GetOffset( ucAddr, ucBase, 6 );
			}
			else if((ucAddr >= 0x04 && ucAddr <= 0x09) )
			{
				*pRegSize	= 6;
				return GetOffset( ucAddr, 0x04, 6 );
			}
		break;
		case B5325_PAGE_ARLA:
			if( 	(ucAddr >= 0x22 && ucAddr <= 0x23) )
			{
				*pRegSize	= 2;
				return GetOffset( ucAddr, 0x22, 2 );
			}
			else if((ucAddr >= 0x02 && ucAddr <= 0x07) )
			{
				*pRegSize	= 6;
				return GetOffset( ucAddr, 0x02, 6 );
			}
			else if((ucAddr >= 0x10 && ucAddr <= 0x1F)
				||	(ucAddr >= 0x24 && ucAddr <= 0x2B) )
			{
				ucBase	= (ucAddr >= 0x24) ? 0x24 : 0x10;
				*pRegSize	= 8;
				return GetOffset( ucAddr, ucBase, 8 );
			}
		break;
		case B5325_PAGE_MFAR:
			if( ucAddr >= 0x02 && ucAddr <= 0x05 )
			{
				*pRegSize	= 2;
				return GetOffset( ucAddr, 0x02, 2 );
			}
		break;
		case B5325_PAGE_GMAR:
			if( ucAddr <= 0x03 )
			{
				*pRegSize	= 4;
				return GetOffset( ucAddr, 0x00, 4 );
			}
			else if( ucAddr >= 0x04 && ucAddr <= 0x0B )
			{
				*pRegSize	= 8;
				return GetOffset( ucAddr, 0x04, 8 );
			}
		break;
		case B5325_PAGE_MIIP(0):
		case B5325_PAGE_MIIP(1):
		case B5325_PAGE_MIIP(2):
		case B5325_PAGE_MIIP(3):
		case B5325_PAGE_MIIP(4):
		case B5325_PAGE_MIP8:
			if( ucAddr >= 0x00 && ucAddr <= 0x3F )
			{
				*pRegSize	= 2;
				return GetOffset( ucAddr, 0x00, 2 );
			}
		break;
		case B5325_PAGE_GMPR:
		break;
		case B5325_PAGE_MIBP(0):
		case B5325_PAGE_MIBP(1):
		case B5325_PAGE_MIBP(2):
		case B5325_PAGE_MIBP(3):
		case B5325_PAGE_MIBP(4):
		case B5325_PAGE_MIB8:
			if( 	(ucAddr >= 0x08 && ucAddr <= 0x3B)
				||	(ucAddr >= 0x4C && ucAddr <= 0x7B)
				||	(ucAddr >= 0x84 && ucAddr <= 0xA3) )
			{
				if(ucAddr >= 0x84)
					ucBase	= 0x84;
				else if(ucAddr >= 0x4C)
					ucBase	= 0x4C;
				else
					ucBase	= 0x08;
				*pRegSize	= 4;
				return GetOffset( ucAddr, ucBase, 4 );
			}
			else if((ucAddr >= 0x00 && ucAddr <= 0x07)
				||	(ucAddr >= 0x44 && ucAddr <= 0x4B)
				||	(ucAddr >= 0x7C && ucAddr <= 0x83) )
			{
				if(ucAddr >= 0x7C)
					ucBase	= 0x7C;
				else if(ucAddr >= 0x44)
					ucBase	= 0x44;
				else
					ucBase	= 0x00;
				*pRegSize	= 8;
				return GetOffset( ucAddr, ucBase, 8 );
			}
		break;
		case B5325_PAGE_QOSR:
			if( 	(ucAddr >= 0x00 && ucAddr <= 0x01)
				||	(ucAddr >= 0x13 && ucAddr <= 0x14) )
			{
				ucBase	= (ucAddr >= 0x13) ? 0x13 : 0x00;
				*pRegSize	= 2;
				return GetOffset( ucAddr, ucBase, 2 );
			}
		break;
		case B5325_PAGE_VLAN:
			if( ucAddr >= 0x00 && ucAddr <= 0x13 )
			{
				*pRegSize	= 2;
				return GetOffset( ucAddr, 0x00, 2 );
			}
		break;
		default:
		break;
	}

	*pRegSize	= 1;
	return 0;
}


/*** BeginHeader EthnetDisp */
xmem void EthnetDisp(void);
/*** EndHeader */
xmem void EthnetDisp(void)
{
	unsigned char ucTmp;
		//////////////////////////////////////1///////////////////////////////////////
	ucTmp = EthRead (0, B5325_PAGE_STAT, B5325_LINK_STAT_SUM(0),6);//ETH_LINK

	ucTmp&0x01  ?   memcpy(FirstUp.Link,"Up\0",5) : memcpy(FirstUp.Link,"Down\0",5);

	ucTmp = EthRead (0, B5325_PAGE_STAT,  B5325_DPLX_STAT_SUM(0),6);//ETH_DPLX

	ucTmp&0x01  ?   memcpy(FirstUp.Model,"Half\0",5):  memcpy(FirstUp.Model,"Full\0",5);

	ucTmp = EthRead (0, B5325_PAGE_STAT, B5325_PORT_SPED_SUM(0),6);//ETH_SPD

	ucTmp&0x01  ?   (FirstUp.Speed=100) : (FirstUp.Speed=10);


     /////////////////////////////////////2/////////////////////////////////////////
	ucTmp = EthRead (0, B5325_PAGE_STAT, B5325_LINK_STAT_SUM(0),7);//ETH_LINK

	ucTmp&0x01  ?   memcpy(FirstData.Link,"Up\0",5) : memcpy(FirstData.Link,"Down\0",5);
	ucTmp&0x02  ?   memcpy(SecondData.Link,"Up\0",5) : memcpy(SecondData.Link,"Down\0",5);

	ucTmp = EthRead (0, B5325_PAGE_STAT,  B5325_DPLX_STAT_SUM(0),7);//ETH_DPLX

	ucTmp&0x01  ?   memcpy(FirstData.Model,"Half\0",5):  memcpy(FirstData.Model,"Full\0",5);
	ucTmp&0x02  ?   memcpy(SecondData.Model,"Half\0",5):  memcpy(SecondData.Model,"Full\0",5);

	ucTmp = EthRead (0, B5325_PAGE_STAT, B5325_PORT_SPED_SUM(0),7);//ETH_SPD

	ucTmp&0x01  ?   (FirstData.Speed=100) : (FirstData.Speed=10);
	ucTmp&0x02  ?   (SecondData.Speed=100) : (SecondData.Speed=10);

	//EthRead (0, B5325_PAGE_STAT,  B5325_LINK_STAT_CHG(0));//ETH_CHG

	//EthRead (1, B5325_PAGE_STAT,  B5325_LINK_STAT_CHG(0));//ETH_CHG
}
/*** BeginHeader EthByteRd */
void EthByteRd( unsigned char ucAddr, unsigned char ucRegSize, unsigned char * pBuf,unsigned char index );
/*** EndHeader */
void EthByteRd( unsigned char ucAddr, unsigned char ucRegSize, unsigned char * pBuf,unsigned char index)
{
	auto unsigned char		i;

	//
	//BitWrPortI( PDDR, &PDDRShadow, 0, 2 );//nconfig
	BitWrPortI( PDDR, &PDDRShadow, 0, index );
	//WrPortI(PDDR,&PDDRShadow,PDDRShadow &(~index));	
	// Command code
	EthWxBits( 0x60 );
	// Address
	EthWxBits( ucAddr );
	// Data
	for( i = 0; i < ucRegSize; ++i )
	{
		pBuf[i]	= EthRxBits( );
	}
	//
	//WrPortI(PDDR,&PDDRShadow,PDDRShadow |index);//CS
	BitWrPortI( PDDR, &PDDRShadow, 1, index );
}

/*** BeginHeader EthByteWt */
void EthByteWt( unsigned char ucAddr, unsigned char ucRegSize, unsigned char * pBuf,unsigned char index );
/*** EndHeader */
void EthByteWt( unsigned char ucAddr, unsigned char ucRegSize, unsigned char * pBuf,unsigned char index )
{
	auto unsigned char		i;

	BitWrPortI( PDDR, &PDDRShadow, 0, index );
	//WrPortI(PDDR,&PDDRShadow,PDDRShadow &(~index));	
	// Command code
	EthWxBits( 0x61 );
	// Address
	EthWxBits( ucAddr );
	// ucBytes
	for( i = 0; i < ucRegSize; i++ )
	{
		EthWxBits( pBuf[i] );
	}
	BitWrPortI( PDDR, &PDDRShadow, 1, index );
	//WrPortI(PDDR,&PDDRShadow,PDDRShadow |index);//CS
}