📄 sam7_flash_ram.ini
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// ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ----------------------------------------------------------------------------
// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ---------------------------------------------------------
// File: SAM7_FLASF_RAM.ini
// User setup file for KEIL debugger
// 1.0 09/Seo/05 JPP : Creation
// ---------------------------------------------------------
//-----------------------------------------------------------------------------
// Remap
//---------
FUNC void CheckRemap(void) {
int i,pt;
i=_RDWORD(0x00000000); //* Read the value at 0x0
i=i+1;
_WDWORD(0x00,i);
pt=_RDWORD(0x00000000);
if (i == pt) {
printf( "------------------------------- The Remap is done ----------------------------------------\n");
} else {
printf( "------------------------------- The Remap is NOT -----------------------------------------\n");
_WDWORD(0xFFFFFF00,0x00000001);//* Toggel RESET The remap
}
}
//-----------------------------------------------------------------------------
// Watchdog
//-------------
// Normally, the Watchdog is enable at the reset for load it's preferable to
// Disable.
//-----------------------------------------------------------------------------
FUNC void Watchdog(void) {
//* Watchdog Disable
_WDWORD(0xFFFFFD44,0x00008000); // AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;
printf( "------------------------------- Watchdog Disable ----------------------------------------\n");
}
//-----------------------------------------------------------------------------
// PllSetting
//-------------------------------
FUNC void PllSetting(void) {
int i;
// -1- Enabling the Main Oscillator:
//*#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
//*#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
//*#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
//*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | //0x0000 0600
// AT91C_CKGR_MOSCEN )); //0x0000 0001
_WDWORD(0xFFFFFC20,0x00000601);
// -3- Setting PLL and divider:
// - div by 14 Fin = 1.3165 =(18,432 / 14)
// - Mul 72+1: Fout = 96.1097 =(3,6864 *73)
// for 96 MHz the erroe is 0.11% Field out NOT USED = 0
// PLLCOUNT pll startup time esrtimate at : 0.844 ms
// PLLCOUNT 28 = 0.000844 /(1/32768)
// pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x0E) | //0x0000 000E
// (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00
// (AT91C_CKGR_MUL & (72<<16))); //0x0048 0000
_WDWORD(0xFFFFFC2C,0x00481C0E);
// -5- Selection of Master Clock and Processor Clock
// select the PLL clock divided by 2
// pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | //0x0000 0003
// AT91C_PMC_PRES_CLK_2 ; //0x0000 0004
_WDWORD(0xFFFFFC30,0x00000007);
printf( "------------------------------- PLL Enable ----------------------------------------\n");
// if ((AT91C_BASE_MC->MC_FSR & AT91C_MC_GPNVM2) == AT91C_MC_GPNVM2 )
i=_RDWORD(0xFFFFFF68);
if (i & 0x400)
{
printf( "------------------------------- GPNVM 2 is already Set------------------------------\n");
} else {
_WDWORD(0xFFFFFF60,0x00300100);
// AT91C_BASE_MC->MC_FCR = AT91C_MC_CORRECT_KEY | AT91C_MC_FCMD_SET_GP_NVM | (AT91C_MC_PAGEN & (gpnvm_bit << 8)) ;
_WDWORD(0xFFFFFF64,0x5A00020B);
printf( "------------------------------- SET GPNVM ------------------------------------------\n");
}
//* #define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
_WDWORD(0xFFFFFF60,0x00480100);
printf( "------------------------------- FLASH Enable ---------------------------------------\n");
}
//-----------------------------------------------------------------------------
// Reset the Interrupt Controller
//-------------------------------
FUNC void AIC(void) {
int i,pt;
_WDWORD(0xFFFFF124,0xFFFFFFFF); // Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
_WDWORD(0xFFFFF128,0xFFFFFFFF); // Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
// Acknownledge timer interrupt
_RDWORD(0xFFFA0020); // #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
_RDWORD(0xFFFA0060); // #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
_RDWORD(0xFFFA00A0); // #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
// disable peripheral clock Peripheral Clock Disable Register
_WDWORD( 0xFFFFFC14,0xFFFFFFFF);
for (i=0;i < 8; i++)
{
pt = _RDWORD(0xFFFFF130); // AT91C_BASE_AIC->AIC_EOICR
}
printf( "------------------------------- AIC 2 INIT ---------------------------------------------\n");
}
FUNC void Setup (void) {
int i;
//* Init AIC
AIC();
PllSetting();
//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area
CheckRemap();
//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
i= _RDWORD(0xFFFFF240);
printf( " ---------------------------------------- Chip ID 0x%08X\n",i);
i=_RDWORD(0xFFFFF244);
printf( " ---------------------------------------- Extention 0x%08X\n",i);
i=_RDWORD(0xFFFFFF6C);
printf( " ------------------------------------ Flash Version 0x%08X\n",i);
//* Watchdog Disable
Watchdog();
}
Setup(); // Setup for Flash Tools
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