xebs.h

开源ZigBee 协议栈

/*************************************************************************
 *                                                                       *
 *       OpenBee v0.1.0 Copyright (c) 2005 OpenBee Project Team          *
 *                                                                       *
 * This file is part of the OpenBee project.                             *
 * The OpenBee project is located at the following                       *
 * location: http://www.openbee.org/                                     *
 *                                                                       *
 * OpenBee is free software. You can redistribute it and/or modify       *
 * it under the terms of the GNU General Public License as published by  *
 * the Free Software Foundation.                                         *
 * See the GNU General Public License for more details:                  *
 * http://opensource.org/licenses/gpl-license.php                        *
 *                                                                       *
 *  *******************************************************************  *
 *  See http://www.openbee.org/ for documentation, latest information,   *
 *  license and contact details.                                         *
 *  *******************************************************************  *
 *                                                                       *
 * The OpenBee project is powered by HEVs (University of Applied         *
 * Sciences Valais): http://www.hevs.edu                                 *
 *                                                                       *
 *************************************************************************/

#ifndef xebs_h
#define xebs_h

/* Flash Memory : AT49BV802AT 1M*8 */
#ifdef RUN_FROM_ROMCOPY
#define FLASH_BASE_BEFORE_REMAP		(0x00000000)	/* Address of flash before remap (boot) */
#define FLASH_BASE					(0x01000000)	/* Address of flash after boot   (main) */												/* Flash stays on this address          */
#elif RUN_FROM_ROMRUN
#define FLASH_BASE_BEFORE_REMAP		(0x00000000)	/* Address of flash before remap (boot) */
#define FLASH_BASE					(0x01000000)	/* Address of flash after boot   (main) */												/* Flash stays on this address          */
#else
#define FLASH_BASE      			(0x01000000)	/* In debug mode RAM is allwas addr 0x00000000 */
#endif


#define FLASH_SIZE      (1*1024*1024)                /* byte */

/* FPGA: XC2S50*/
#ifdef RUN_FROM_ROMCOPY
	#define FPGA_BASE 		(0x02000000)
#elif RUN_FROM_ROMRUN
	#define FPGA_BASE		(0x02000000)
#else
	#define FPGA_BASE 		(0x02000000)
#endif

/***************
*  WARNING !!!*
***************
*- WARNING !! No External SRAM memories are fitted on the board.
*- This definition is only if the user adds external SRAM devices.

* The following definition are put in comments
*/
#define RAM_BASE_BEFORE_REMAP	(0x00300000)    /* Address of the Internal SRAM before remap command */
#define RAM_BASE     			(0x00000000)    /* Address of the Internal SRAM after the remap command */
#define RAM_SIZE     			(256*1024)

/***************
* WARNING !!! *  The RAM_LIMIT definition does not correspond to ( RAM_BASE + RAM_SIZE )
***************

* This is for compatipility with the cstartup_xxx.ads (flash, ice or angel).
*/
#define RAM_LIMIT     (RAM_BASE + (8*1024))       /* Size of the Application stack is 8K. */

/*
 * Redefinition of External SRAM to Internal SRAM
 */

#define EXT_SRAM_BASE       RAM_LIMIT                   /* 8K (8*1024) */
#define EXT_SRAM_SIZE       (RAM_SIZE-RAM_LIMIT)        /* 256K (256*1024) - 8K (8*1024) */
#define EXT_SRAM_LIMIT      (RAM_BASE + RAM_SIZE)       /* = SRAM_LIMIT = 0x40000 */

/*
 * OpenBeeDK external SRAM
 */
#define SRAM1_BASE		(0x03000000)
#define SRAM1_SIZE		(512*1024)

/*
 * Chipselect Registers
 */
#define EBI_CSR_0       ((unsigned int )(FLASH_BASE | 0x312D))    /* 0x01000000, 16MB, 4 wait states, 0 cycles added after transfer, 16-bit, byte select */
#define EBI_CSR_1       ((unsigned int )(FPGA_BASE  | 0x312D))    /* 0x02000000, 16MB, 4 wait states, 0 cycles added after transfer, 16-bit, byte select */
#define EBI_CSR_2       ((unsigned int )(SRAM1_BASE | 0x3121))    /* 0x03000000, 16MB, 0 wait states, 0 cycles added after transfer, 16-bit, byte select */
#define EBI_CSR_3       ((unsigned int )0x40000000)               /* unused */
#define EBI_CSR_4       ((unsigned int )0x50000000)               /* unused */
#define EBI_CSR_5       ((unsigned int )0x60000000)               /* unused */
#define EBI_CSR_6       ((unsigned int )0x70000000)               /* unused */
#define EBI_CSR_7       ((unsigned int )0x80000000)               /* unused */

/* 16M bytes per Chip Select. Early read protocol */
#define EBI_MCR_VALUE	(0x00000000)

/*
 * Master Clock
 */
#define MCK             48000000
#define MCKKHz          (MCK/1000)

#endif /* xebs_h */