at91r40008.h

开源ZigBee 协议栈

#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFE0040) // (TC1) Channel Control Register
#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFE006C) // (TC1) Interrupt Mask Register
#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFE0064) // (TC1) Interrupt Enable Register
#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFE005C) // (TC1) Register C
#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFE0054) // (TC1) Register A
#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFE0044) // (TC1) Channel Mode Register
// ========== Register definition for TC0 peripheral ========== 
#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFE0028) // (TC0) Interrupt Disable Register
#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFE0020) // (TC0) Status Register
#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFE0018) // (TC0) Register B
#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFE0010) // (TC0) Counter Value
#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFE0000) // (TC0) Channel Control Register
#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFE002C) // (TC0) Interrupt Mask Register
#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFE0024) // (TC0) Interrupt Enable Register
#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFE001C) // (TC0) Register C
#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFE0014) // (TC0) Register A
#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFE0004) // (TC0) Channel Mode Register
// ========== Register definition for TCB0 peripheral ========== 
#define AT91C_TCB0_BCR  ((AT91_REG *) 	0xFFFE00C0) // (TCB0) TC Block Control Register
#define AT91C_TCB0_BMR  ((AT91_REG *) 	0xFFFE00C4) // (TCB0) TC Block Mode Register
// ========== Register definition for PDC_US1 peripheral ========== 
#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4038) // (PDC_US1) Transmit Pointer Register
#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4030) // (PDC_US1) Receive Pointer Register
#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC403C) // (PDC_US1) Transmit Counter Register
#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4034) // (PDC_US1) Receive Counter Register
// ========== Register definition for US1 peripheral ========== 
#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFCC024) // (US1) Receiver Time-out Register
#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFCC01C) // (US1) Transmitter Holding Register
#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFCC014) // (US1) Channel Status Register
#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFCC00C) // (US1) Interrupt Disable Register
#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFCC004) // (US1) Mode Register
#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFCC028) // (US1) Transmitter Time-guard Register
#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFCC020) // (US1) Baud Rate Generator Register
#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFCC018) // (US1) Receiver Holding Register
#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFCC010) // (US1) Interrupt Mask Register
#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFCC008) // (US1) Interrupt Enable Register
#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFCC000) // (US1) Control Register
// ========== Register definition for PDC_US0 peripheral ========== 
#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0038) // (PDC_US0) Transmit Pointer Register
#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0030) // (PDC_US0) Receive Pointer Register
#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC003C) // (PDC_US0) Transmit Counter Register
#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0034) // (PDC_US0) Receive Counter Register
// ========== Register definition for US0 peripheral ========== 
#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFD0024) // (US0) Receiver Time-out Register
#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFD001C) // (US0) Transmitter Holding Register
#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFD0014) // (US0) Channel Status Register
#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFD000C) // (US0) Interrupt Disable Register
#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFD0004) // (US0) Mode Register
#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFD0028) // (US0) Transmitter Time-guard Register
#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFD0020) // (US0) Baud Rate Generator Register
#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFD0018) // (US0) Receiver Holding Register
#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFD0010) // (US0) Interrupt Mask Register
#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFD0008) // (US0) Interrupt Enable Register
#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFD0000) // (US0) Control Register
// ========== Register definition for SF peripheral ========== 
#define AT91C_SF_PMR    ((AT91_REG *) 	0xFFF00018) // (SF) Protect Mode Register
#define AT91C_SF_RSR    ((AT91_REG *) 	0xFFF00008) // (SF) Reset Status Register
#define AT91C_SF_CIDR   ((AT91_REG *) 	0xFFF00000) // (SF) Chip ID Register
#define AT91C_SF_MMR    ((AT91_REG *) 	0xFFF0000C) // (SF) Memory Mode Register
#define AT91C_SF_EXID   ((AT91_REG *) 	0xFFF00004) // (SF) Chip ID Extension Register
// ========== Register definition for EBI peripheral ========== 
#define AT91C_EBI_RCR   ((AT91_REG *) 	0xFFE00020) // (EBI) Remap Control Register
#define AT91C_EBI_CSR   ((AT91_REG *) 	0xFFE00000) // (EBI) Chip-select Register
#define AT91C_EBI_MCR   ((AT91_REG *) 	0xFFE00024) // (EBI) Memory Control Register

// *****************************************************************************
//               PIO DEFINITIONS FOR AT91R40008
// *****************************************************************************
#define AT91C_PIO_P0         ((unsigned int) 1 <<  0) // Pin Controlled by P0
#define AT91C_P0_TCLK0    ((unsigned int) AT91C_PIO_P0) //  Timer 0 Clock signal
#define AT91C_PIO_P1         ((unsigned int) 1 <<  1) // Pin Controlled by P1
#define AT91C_P1_TIOA0    ((unsigned int) AT91C_PIO_P1) //  Timer 0 Signal A
#define AT91C_PIO_P10        ((unsigned int) 1 << 10) // Pin Controlled by P10
#define AT91C_P10_IRQ1     ((unsigned int) AT91C_PIO_P10) //  External Interrupt 1
#define AT91C_PIO_P11        ((unsigned int) 1 << 11) // Pin Controlled by P11
#define AT91C_P11_IRQ2     ((unsigned int) AT91C_PIO_P11) //  External Interrupt 2
#define AT91C_PIO_P12        ((unsigned int) 1 << 12) // Pin Controlled by P12
#define AT91C_P12_FIQ      ((unsigned int) AT91C_PIO_P12) //  Fast External Interrupt
#define AT91C_PIO_P13        ((unsigned int) 1 << 13) // Pin Controlled by P13
#define AT91C_P13_SCK0     ((unsigned int) AT91C_PIO_P13) //  USART 0 Serial Clock
#define AT91C_PIO_P14        ((unsigned int) 1 << 14) // Pin Controlled by P14
#define AT91C_P14_TXD0     ((unsigned int) AT91C_PIO_P14) //  USART 0 Transmit Data
#define AT91C_PIO_P15        ((unsigned int) 1 << 15) // Pin Controlled by P15
#define AT91C_P15_RXD0     ((unsigned int) AT91C_PIO_P15) //  USART 0 Receive Data
#define AT91C_PIO_P16        ((unsigned int) 1 << 16) // Pin Controlled by P16
#define AT91C_PIO_P17        ((unsigned int) 1 << 17) // Pin Controlled by P17
#define AT91C_PIO_P18        ((unsigned int) 1 << 18) // Pin Controlled by P18
#define AT91C_PIO_P19        ((unsigned int) 1 << 19) // Pin Controlled by P19
#define AT91C_PIO_P2         ((unsigned int) 1 <<  2) // Pin Controlled by P2
#define AT91C_P2_TIOB0    ((unsigned int) AT91C_PIO_P2) //  Timer 0 Signal B
#define AT91C_PIO_P20        ((unsigned int) 1 << 20) // Pin Controlled by P20
#define AT91C_P20_SCK1     ((unsigned int) AT91C_PIO_P20) //  USART 1 Serial Clock
#define AT91C_PIO_P21        ((unsigned int) 1 << 21) // Pin Controlled by P21
#define AT91C_P21_TXD1     ((unsigned int) AT91C_PIO_P21) //  USART 1 Transmit Data
#define AT91C_P21_NTRI     ((unsigned int) AT91C_PIO_P21) //  Tri-state Mode
#define AT91C_PIO_P22        ((unsigned int) 1 << 22) // Pin Controlled by P22
#define AT91C_P22_RXD1     ((unsigned int) AT91C_PIO_P22) //  USART 1 Receive Data
#define AT91C_PIO_P23        ((unsigned int) 1 << 23) // Pin Controlled by P23
#define AT91C_PIO_P24        ((unsigned int) 1 << 24) // Pin Controlled by P24
#define AT91C_P24_BMS      ((unsigned int) AT91C_PIO_P24) //  Boot Mode Select
#define AT91C_PIO_P25        ((unsigned int) 1 << 25) // Pin Controlled by P25
#define AT91C_P25_MCKO     ((unsigned int) AT91C_PIO_P25) //  Master Clock Out
#define AT91C_PIO_P26        ((unsigned int) 1 << 26) // Pin Controlled by P26
#define AT91C_P26_NCS2     ((unsigned int) AT91C_PIO_P26) //  Chip Select 2
#define AT91C_PIO_P27        ((unsigned int) 1 << 27) // Pin Controlled by P27
#define AT91C_P27_NCS3     ((unsigned int) AT91C_PIO_P27) //  Chip Select 3
#define AT91C_PIO_P28        ((unsigned int) 1 << 28) // Pin Controlled by P28
#define AT91C_P28_A20      ((unsigned int) AT91C_PIO_P28) //  Address line A20
#define AT91C_P28_NCS7     ((unsigned int) AT91C_PIO_P28) //  Chip Select 7
#define AT91C_PIO_P29        ((unsigned int) 1 << 29) // Pin Controlled by P29
#define AT91C_P29_A21      ((unsigned int) AT91C_PIO_P29) //  Address line A21
#define AT91C_P29_NCS6     ((unsigned int) AT91C_PIO_P29) //  Chip Select 6
#define AT91C_PIO_P3         ((unsigned int) 1 <<  3) // Pin Controlled by P3
#define AT91C_P3_TCLK1    ((unsigned int) AT91C_PIO_P3) //  Timer 1 Clock signal
#define AT91C_PIO_P30        ((unsigned int) 1 << 30) // Pin Controlled by P30
#define AT91C_P30_A22      ((unsigned int) AT91C_PIO_P30) //  Address line A22
#define AT91C_P30_NCS5     ((unsigned int) AT91C_PIO_P30) //  Chip Select 5
#define AT91C_PIO_P31        ((unsigned int) 1 << 31) // Pin Controlled by P31
#define AT91C_P31_A23      ((unsigned int) AT91C_PIO_P31) //  Address line A23
#define AT91C_P31_NCS4     ((unsigned int) AT91C_PIO_P31) //  Chip Select 4
#define AT91C_PIO_P4         ((unsigned int) 1 <<  4) // Pin Controlled by P4
#define AT91C_P4_TIOA1    ((unsigned int) AT91C_PIO_P4) //  Timer 1 Signal A
#define AT91C_PIO_P5         ((unsigned int) 1 <<  5) // Pin Controlled by P5
#define AT91C_P5_TIOB1    ((unsigned int) AT91C_PIO_P5) //  Timer 1 Signal B
#define AT91C_PIO_P6         ((unsigned int) 1 <<  6) // Pin Controlled by P6
#define AT91C_P6_TCLK2    ((unsigned int) AT91C_PIO_P6) //  Timer 2 Clock signal
#define AT91C_PIO_P7         ((unsigned int) 1 <<  7) // Pin Controlled by P7
#define AT91C_P7_TIOA2    ((unsigned int) AT91C_PIO_P7) //  Timer 2 Signal A
#define AT91C_PIO_P8         ((unsigned int) 1 <<  8) // Pin Controlled by P8
#define AT91C_P8_TIOB2    ((unsigned int) AT91C_PIO_P8) //  Timer 2 Signal B
#define AT91C_PIO_P9         ((unsigned int) 1 <<  9) // Pin Controlled by P9
#define AT91C_P9_IRQ0     ((unsigned int) AT91C_PIO_P9) //  External Interrupt 0

// *****************************************************************************
//               PERIPHERAL ID DEFINITIONS FOR AT91R40008
// *****************************************************************************
#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
#define AT91C_ID_SYS    ((unsigned int)  1) // SWI
#define AT91C_ID_US0    ((unsigned int)  2) // USART 0
#define AT91C_ID_US1    ((unsigned int)  3) // USART 1
#define AT91C_ID_TC0    ((unsigned int)  4) // Timer Counter 0
#define AT91C_ID_TC1    ((unsigned int)  5) // Timer Counter 1
#define AT91C_ID_TC2    ((unsigned int)  6) // Timer Counter 2
#define AT91C_ID_WD     ((unsigned int)  7) // Watchdog Timer
#define AT91C_ID_PIO    ((unsigned int)  8) // Parallel IO Controller
#define AT91C_ID_IRQ0   ((unsigned int) 16) // Advanced Interrupt Controller (IRQ0)
#define AT91C_ID_IRQ1   ((unsigned int) 17) // Advanced Interrupt Controller (IRQ1)
#define AT91C_ID_IRQ2   ((unsigned int) 18) // Advanced Interrupt Controller (IRQ2)

// *****************************************************************************
//               BASE ADDRESS DEFINITIONS FOR AT91R40008
// *****************************************************************************
#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
#define AT91C_BASE_WD        ((AT91PS_WD) 	0xFFFF8000) // (WD) Base Address
#define AT91C_BASE_PS        ((AT91PS_PS) 	0xFFFF4000) // (PS) Base Address
#define AT91C_BASE_PIO       ((AT91PS_PIO) 	0xFFFF0000) // (PIO) Base Address
#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFE0080) // (TC2) Base Address
#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFE0040) // (TC1) Base Address
#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFE0000) // (TC0) Base Address
#define AT91C_BASE_TCB0      ((AT91PS_TCB) 	0xFFFE0000) // (TCB0) Base Address
#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4030) // (PDC_US1) Base Address
#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFCC000) // (US1) Base Address
#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0030) // (PDC_US0) Base Address
#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFD0000) // (US0) Base Address
#define AT91C_BASE_SF        ((AT91PS_SF) 	0xFFF00000) // (SF) Base Address
#define AT91C_BASE_EBI       ((AT91PS_EBI) 	0xFFE00000) // (EBI) Base Address

// *****************************************************************************
//               MEMORY MAPPING DEFINITIONS FOR AT91R40008
// *****************************************************************************
#define AT91C_SRAM_BEFORE_REMAP	 ((char *) 	0x00300000) // Internal SRAM before remap base address
#define AT91C_SRAM_BEFORE_REMAP_SIZE	 ((unsigned int) 0x00040000) // Internal SRAM before remap size in byte (256 Kbyte)
#define AT91C_SRAM_AFTER_REMAP	 ((char *) 	0x00000000) // Internal SRAM after remap base address
#define AT91C_SRAM_AFTER_REMAP_SIZE	 ((unsigned int) 0x00040000) // Internal SRAM after remap size in byte (256 Kbyte)

#endif