📄 uart.lst
字号:
0000006C E1A03C23 MOV R3,R3,LSR #24
00000070 E5101000 LDR R1,=UART0Status ; UART0Status
00000074 E5813000 STR R3,[R1,#0x0] ; UART0Status
50: Dummy = U0RBR; /* Dummy read on RX to clear
00000078 E5101000 LDR R1,=0xE000C000
0000007C E5911000 LDR R1,[R1,#0x0]
52: IDISABLE;
00000080 E8BD4000 LDMFD R13!,{LR}
00000084 E321F092 MSR CPSR_c,#0x92
00000088 E8BD4000 LDMFD R13!,{LR}
0000008C E16FF00E MSR SPSR_cxsf,R14
53: VICVectAddr = 0; /* Acknowledge Interrupt */
00000090 E3A03000 MOV R3,#0x0
00000094 E5101000 LDR R1,=0xFFFFF030
00000098 E5813000 STR R3,[R1,#0x0]
54: return;
0000009C EA000058 B L_3 ; Targ=0x204
55: }
000000A0 L_2:
56: if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
000000A0 E1A01000 MOV R1,R0 ; LSRValue
000000A4 E1A01C01 MOV R1,R1,LSL #24 ; LSRValue
000000A8 E1A01C21 MOV R1,R1,LSR #24
000000AC E3110001 TST R1,#0x0001
000000B0 0A00004C BEQ L_6 ; Targ=0x1E8
60: UART0Buffer[UART0Count] = U0RBR;
000000B4 E5101000 LDR R1,=0xE000C000
000000B8 E5911000 LDR R1,[R1,#0x0]
000000BC E1A01C01 MOV R1,R1,LSL #24
000000C0 E1A01C21 MOV R1,R1,LSR #24
000000C4 E5103000 LDR R3,=UART0Count ; UART0Count
000000C8 E5933000 LDR R3,[R3,#0x0] ; UART0Count
000000CC E1A05003 MOV R5,R3
000000D0 E5104000 LDR R4,=UART0Buffer ; UART0Buffer
000000D4 E7C41005 STRB R1,[R4,+R5]
61: UART0Count++;
000000D8 E5101000 LDR R1,=UART0Count ; UART0Count
000000DC E2833001 ADD R3,R3,#0x0001
000000E0 E5813000 STR R3,[R1,#0x0] ; UART0Count
62: if ( UART0Count == BUFSIZE )
000000E4 E5101000 LDR R1,=UART0Count ; UART0Count
000000E8 E5911000 LDR R1,[R1,#0x0] ; UART0Count
000000EC E3510010 CMP R1,#0x0010
000000F0 1A00003C BNE L_6 ; Targ=0x1E8
64: UART0Count = 0; /* buffer overflow */
000000F4 E3A03000 MOV R3,#0x0
000000F8 E5101000 LDR R1,=UART0Count ; UART0Count
000000FC E5813000 STR R3,[R1,#0x0] ; UART0Count
67: }
ARM COMPILER V2.53, uart 02/08/06 09:01:33 PAGE 6
00000100 EA000038 B L_6 ; Targ=0x1E8
00000104 L_1:
68: else if ( IIRValue == IIR_RDA ) /* Receive Data Available */
00000104 E1A01002 MOV R1,R2 ; IIRValue
00000108 E1A01C01 MOV R1,R1,LSL #24 ; IIRValue
0000010C E1A01C21 MOV R1,R1,LSR #24
00000110 E3510002 CMP R1,#0x0002
00000114 1A000013 BNE L_7 ; Targ=0x168
71: UART0Buffer[UART0Count] = U0RBR;
00000118 E5101000 LDR R1,=0xE000C000
0000011C E5911000 LDR R1,[R1,#0x0]
00000120 E1A01C01 MOV R1,R1,LSL #24
00000124 E1A01C21 MOV R1,R1,LSR #24
00000128 E5103000 LDR R3,=UART0Count ; UART0Count
0000012C E5933000 LDR R3,[R3,#0x0] ; UART0Count
00000130 E1A05003 MOV R5,R3
00000134 E5104000 LDR R4,=UART0Buffer ; UART0Buffer
00000138 E7C41005 STRB R1,[R4,+R5]
72: UART0Count++;
0000013C E5101000 LDR R1,=UART0Count ; UART0Count
00000140 E2833001 ADD R3,R3,#0x0001
00000144 E5813000 STR R3,[R1,#0x0] ; UART0Count
73: if ( UART0Count == BUFSIZE )
00000148 E5101000 LDR R1,=UART0Count ; UART0Count
0000014C E5911000 LDR R1,[R1,#0x0] ; UART0Count
00000150 E3510010 CMP R1,#0x0010
00000154 1A000023 BNE L_6 ; Targ=0x1E8
75: UART0Count = 0; /* buffer overflow */
00000158 E3A03000 MOV R3,#0x0
0000015C E5101000 LDR R1,=UART0Count ; UART0Count
00000160 E5813000 STR R3,[R1,#0x0] ; UART0Count
77: }
00000164 EA00001F B L_6 ; Targ=0x1E8
00000168 L_7:
78: else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */
00000168 E1A01002 MOV R1,R2 ; IIRValue
0000016C E1A01C01 MOV R1,R1,LSL #24 ; IIRValue
00000170 E1A01C21 MOV R1,R1,LSR #24
00000174 E3510006 CMP R1,#0x0006
00000178 1A000005 BNE L_10 ; Targ=0x194
81: UART0Status |= 0x100; /* Bit 9 as the CTI error */
0000017C E5101000 LDR R1,=UART0Status ; UART0Status
00000180 E5913000 LDR R3,[R1,#0x0] ; UART0Status
00000184 E3833C01 ORR R3,R3,#0x0100
00000188 E5101000 LDR R1,=UART0Status ; UART0Status
0000018C E5813000 STR R3,[R1,#0x0] ; UART0Status
82: }
00000190 EA000014 B L_6 ; Targ=0x1E8
00000194 L_10:
83: else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */
00000194 E1A01002 MOV R1,R2 ; IIRValue
00000198 E1A01C01 MOV R1,R1,LSL #24 ; IIRValue
0000019C E1A01C21 MOV R1,R1,LSR #24
000001A0 E3510001 CMP R1,#0x0001
000001A4 1A00000F BNE L_6 ; Targ=0x1E8
86: LSRValue = U0LSR; /* Check status in the LSR to see if
000001A8 E5100000 LDR R0,=0xE000C014
000001AC E5900000 LDR R0,[R0,#0x0]
000001B0 E1A00C00 MOV R0,R0,LSL #24
000001B4 E1A00C20 MOV R0,R0,LSR #24
88: if ( LSRValue & LSR_THRE )
000001B8 E1A01000 MOV R1,R0 ; LSRValue
000001BC E1A01C01 MOV R1,R1,LSL #24 ; LSRValue
000001C0 E1A01C21 MOV R1,R1,LSR #24
000001C4 E3110020 TST R1,#0x0020
000001C8 0A000003 BEQ L_13 ; Targ=0x1DC
ARM COMPILER V2.53, uart 02/08/06 09:01:33 PAGE 7
90: UART0TxEmpty = 1;
000001CC E3A02001 MOV R2,#0x1
000001D0 E5101000 LDR R1,=UART0TxEmpty ; UART0TxEmpty
000001D4 E5C12000 STRB R2,[R1,#0x0] ; UART0TxEmpty
91: }
000001D8 EA000002 B L_6 ; Targ=0x1E8
000001DC L_13:
94: UART0TxEmpty = 0;
000001DC E3A02000 MOV R2,#0x0
000001E0 E5101000 LDR R1,=UART0TxEmpty ; UART0TxEmpty
000001E4 E5C12000 STRB R2,[R1,#0x0] ; UART0TxEmpty
96: }
000001E8 L_6:
98: IDISABLE;
000001E8 E8BD4000 LDMFD R13!,{LR}
000001EC E321F092 MSR CPSR_c,#0x92
000001F0 E8BD4000 LDMFD R13!,{LR}
000001F4 E16FF00E MSR SPSR_cxsf,R14
99: VICVectAddr = 0; /* Acknowledge Interrupt */
000001F8 E3A02000 MOV R2,#0x0
000001FC E5101000 LDR R1,=0xFFFFF030
00000200 E5812000 STR R2,[R1,#0x0]
00000204 ; SCOPE-END
100: }
00000204 L_3:
00000204 E8BD403F LDMIA R13!,{R0-R5,LR}
00000208 E25EF004 SUBS R15,R14,#0x0004
0000020C ENDP ; 'UART0Handler?A'
*** CODE SEGMENT '?PR?UARTInit?T?uart':
114: DWORD UARTInit( DWORD baudrate )
00000000 B500 PUSH {LR}
00000002 1C02 MOV R2,R0 ; baudrate
00000004 ---- Variable 'baudrate' assigned to Register 'R2' ----
115: {
00000004 ; SCOPE-START
118: PINSEL0 = 0x00050005; /* 允许 RxD1 和TxD1, RxD0 和TxD0 */
00000004 4800 LDR R1,=0x50005
00000006 4800 LDR R0,=0xE002C000
00000008 6001 STR R1,[R0,#0x0]
120: U0LCR = 0x83; /* 8 位,无奇偶校验, 一位停止位 */
0000000A 2183 MOV R1,#0x83
0000000C 4800 LDR R0,=0xE000C00C
0000000E 6001 STR R1,[R0,#0x0]
121: Fdiv = ( Fpclk / 16 ) / baudrate ; /*波特率 */
00000010 1C11 MOV R1,R2 ; baudrate
00000012 4800 LDR R0,=0xE4E1C
00000014 F7FF BL ?C?UDIV?T ; T=0x0001 (1) ; ?C?UDIV?T
00000016 FFF4 BL ?C?UDIV?T ; T=0x0001 (2) ; ?C?UDIV?T
00000018 1C08 MOV R0,R1
0000001A 1C02 MOV R2,R0 ; Fdiv
0000001C ---- Variable 'Fdiv' assigned to Register 'R2' ----
122: U0DLM = Fdiv / 256;
0000001C 1C11 MOV R1,R2 ; Fdiv
0000001E 0A09 LSR R1,R1,#0x8 ; Fdiv
00000020 4800 LDR R0,=0xE000C004
00000022 6001 STR R1,[R0,#0x0]
123: U0DLL = Fdiv % 256;
00000024 1C11 MOV R1,R2 ; Fdiv
00000026 20FF MOV R0,#0xFF
00000028 4001 AND R1,R0
0000002A 4800 LDR R0,=0xE000C000
0000002C 6001 STR R1,[R0,#0x0]
124: U0LCR = 0x03; /* DLAB = 0 */
0000002E 2103 MOV R1,#0x3
00000030 4800 LDR R0,=0xE000C00C
00000032 6001 STR R1,[R0,#0x0]
ARM COMPILER V2.53, uart 02/08/06 09:01:33 PAGE 8
125: U0FCR = 0x07; /* 允许复位 TX 和RX FIFO. */
00000034 2107 MOV R1,#0x7
00000036 4800 LDR R0,=0xE000C008
00000038 6001 STR R1,[R0,#0x0]
127: if ( install_irq( UART0_INT, (void *)UART0Handler ) == FALSE )
0000003A 4900 LDR R1,=UART0Handler?A ; UART0Handler?A
0000003C 2006 MOV R0,#0x6
0000003E F7FF BL install_irq?T ; T=0x0001 (1)
00000040 FFDF BL install_irq?T ; T=0x0001 (2)
00000042 2800 CMP R0,#0x0 ; install_irq?T
00000044 D101 BNE L_15 ; T=0x0000004A
129: return (FALSE);
00000046 2000 MOV R0,#0x0
00000048 E003 B L_16 ; T=0x00000052
130: }
0000004A L_15:
132: U0IER = IER_RBR | IER_THRE | IER_RLS; /* 允许UART0中断*/
0000004A 2107 MOV R1,#0x7
0000004C 4800 LDR R0,=0xE000C004
0000004E 6001 STR R1,[R0,#0x0]
133: return (TRUE);
00000050 2001 MOV R0,#0x1
00000052 ; SCOPE-END
134: }
00000052 L_16:
00000052 BC08 POP {R3}
00000054 4718 BX R3
00000056 ENDP ; 'UARTInit?T'
*** CODE SEGMENT '?PR?UARTSend?T?uart':
146: void UARTSend(BYTE *BufferPtr, DWORD Length )
00000000 ---- Variable 'Length' assigned to Register 'R1' ----
00000000 ---- Variable 'BufferPtr' assigned to Register 'R0' ----
148: while ( Length != 0 )
00000000 E00D B L_17 ; T=0x0000001E
150: while ( !(UART0TxEmpty & 0x01) ); /* THRE status, contain valid
00000002 L_24:
00000002 L_21:
00000002 4800 LDR R2,=UART0TxEmpty ; UART0TxEmpty
00000004 7812 LDRB R2,[R2,#0x0] ; UART0TxEmpty
00000006 2301 MOV R3,#0x1
00000008 421A TST R2,R3
0000000A D0FA BEQ L_21 ; T=0x00000002
152: U0THR = *BufferPtr;
0000000C 1C02 MOV R2,R0 ; BufferPtr
0000000E 7813 LDRB R3,[R2,#0x0] ; BufferPtr
00000010 4800 LDR R2,=0xE000C000
00000012 6013 STR R3,[R2,#0x0]
153: UART0TxEmpty = 0; /* not empty in the THR until it shifts out */
00000014 2300 MOV R3,#0x0
00000016 4800 LDR R2,=UART0TxEmpty ; UART0TxEmpty
00000018 7013 STRB R3,[R2,#0x0] ; UART0TxEmpty
154: BufferPtr++;
0000001A 3001 ADD R0,#0x1
155: Length--;
0000001C 3901 SUB R1,#0x1
156: }
0000001E L_17:
0000001E 1C0A MOV R2,R1 ; Length
00000020 2A00 CMP R2,#0x0 ; Length
00000022 D1EE BNE L_24 ; T=0x00000002
158: }
00000024 4770 BX R14
00000026 ENDP ; 'UARTSend?T'
Module Information Static
----------------------------------
ARM COMPILER V2.53, uart 02/08/06 09:01:33 PAGE 9
code size = ------
data size = 25
const size = ------
End of Module Information.
ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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