list_prim_delays_test.log

来自「pli_handbook_examples_pc verilog hdl 与C」· LOG 代码 · 共 51 行

Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
    list_prim_delays_test.v

Verilog_XL_Turbo_NT 2.6.9 log file created Jan  9, 1999  11:05:42
Verilog_XL_Turbo_NT 2.6.9   Jan  9, 1999  11:05:42

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Compiling source file "list_prim_delays_test.v"
Highest level modules:
top


Primitives in module top.i1:
  xor      instance p1  :  rise=1.87, fall=1.87
  xor      instance p2  :  rise=1.80, fall=2.20
  and      instance p3  :  rise=0.00, fall=0.00
  and      instance p4  :  rise=0.00, fall=0.00
  or       instance p5  :  rise=4.00, fall=4.00
  bufif1   instance p6  :  rise=2.00, fall=5.00, toZ=8.00
L22 "list_prim_delays_test.v": $finish at simulation time 200
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.7 secs to compile + 0.0 secs to link + 0.0 secs in simulation
End of Verilog_XL_Turbo_NT 2.6.9   Jan  9, 1999  11:05:43