hello_test.v

来自「pli_handbook_examples_pc verilog hdl 与C」· Verilog 代码 · 共 22 行

/**********************************************************************
 * $hello example -- Verilog HDL test bench.
 *
 * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
 *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
 *   Contact: www.wkap.il
 *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
 *   Contact: www.sutherland.com or [phone]
 *********************************************************************/
`timescale 1ns / 1ns
module test;

  initial
    begin
      $hello;
      #10 $stop;
      $finish;
    end
endmodule
/**********************************************************************/