read_vector_test.log

pli_handbook_examples_pc verilog hdl 与C的接口的典型例子

Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
    read_vector_test.v

Verilog_XL_Turbo_NT 2.6.9 log file created Dec 23, 1998  19:57:23
Verilog_XL_Turbo_NT 2.6.9   Dec 23, 1998  19:57:23

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Compiling source file "read_vector_test.v"
Highest level modules:
test

at          0: clk = 0  vector = xxxxxxxx
at         10: clk = 1  vector = 00000000
at         20: clk = 0  vector = 01010101
at         30: clk = 1  vector = 00001111
at         40: clk = 0  vector = 10101010
at         50: clk = 1  vector = 11110000
at         60: clk = 0  vector = zzzzzzzz
at         70: clk = 1  vector = 11111111
at         80: clk = 0  vector = 1xz01xz0
at         90: clk = 1  vector = 00000000
at        100: clk = 0  vector = 01010101
at        110: clk = 1  vector = 00001111
at        120: clk = 0  vector = 10101010
at        130: clk = 1  vector = 11110000
at        140: clk = 0  vector = zzzzzzzz
at        150: clk = 1  vector = 11111111
at        160: clk = 0  vector = 1xz01xz0
"read_vector_test.v", 25: warning! $read_test_vector reached End-Of-File read_vector_test1.pat
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.7 secs to compile + 0.0 secs to link + 0.8 secs in simulation
End of Verilog_XL_Turbo_NT 2.6.9   Dec 23, 1998  19:57:24