show_all_nets_test.log

来自「pli_handbook_examples_pc verilog hdl 与C」· LOG 代码 · 共 56 行

Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
    show_all_nets_test.v

Verilog_XL_Turbo_NT 2.6.9 log file created Nov 24, 1998  21:23:36
Verilog_XL_Turbo_NT 2.6.9   Nov 24, 1998  21:23:36

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Compiling source file "show_all_nets_test.v"
Highest level modules:
top


At time 2.00, nets in module top (top):
  net results     value is  10 (binary)

At time 3.00, nets in module top.i1 (addbit):
  net a           value is  1 (binary)
  net b           value is  1 (binary)
  net ci          value is  0 (binary)
  net sum         value is  0 (binary)
  net co          value is  1 (binary)
  net n1          value is  0 (binary)
  net n2          value is  1 (binary)
  net n3          value is  0 (binary)
L29 "show_all_nets_test.v": $finish at simulation time 4
0 simulation events (use +profile or +listcounts option to count) + 12 accelerated events
CPU time: 0.7 secs to compile + 0.5 secs to link + 0.1 secs in simulation
End of Verilog_XL_Turbo_NT 2.6.9   Nov 24, 1998  21:23:37