at91rm9200.h

为At91rm9200制作的cs8900驱动

// ----------------------------------------------------------------------------
//          ATMEL Microcontroller Software Support  -  ROUSSET  -
// ----------------------------------------------------------------------------
//  The software is delivered "AS IS" without warranty or condition of any
//  kind, either express, implied or statutory. This includes without
//  limitation any warranty or condition with respect to merchantability or
//  fitness for any particular purpose, or against the infringements of
//  intellectual property rights of others.
// ----------------------------------------------------------------------------
// File Name           : AT91RM9200.h
// Object              : AT91RM9200 definitions
// Generated           : AT91 SW Application Group  04/16/2003 (12:30:06)
//
// ----------------------------------------------------------------------------

#ifndef AT91RM9200_H
#define AT91RM9200_H

#ifndef __ASSEMBLY__

 /* Hardware register definition */
typedef volatile unsigned int AT91_REG;

#endif	/* __ASSEMBLY__ */

// *****************************************************************************
//               PERIPHERAL ID DEFINITIONS FOR AT91RM9200
// *****************************************************************************
#define AT91C_ID_FIQ    ( 0) // Advanced Interrupt Controller (FIQ)
#define AT91C_ID_SYS    ( 1) // System Peripheral
#define AT91C_ID_PIOA   ( 2) // Parallel IO Controller A
#define AT91C_ID_PIOB   ( 3) // Parallel IO Controller B
#define AT91C_ID_PIOC   ( 4) // Parallel IO Controller C
#define AT91C_ID_PIOD   ( 5) // Parallel IO Controller D
#define AT91C_ID_US0    ( 6) // USART 0
#define AT91C_ID_US1    ( 7) // USART 1
#define AT91C_ID_US2    ( 8) // USART 2
#define AT91C_ID_US3    ( 9) // USART 3
#define AT91C_ID_MCI    (10) // Multimedia Card Interface
#define AT91C_ID_UDP    (11) // USB Device Port
#define AT91C_ID_TWI    (12) // Two-Wire Interface
#define AT91C_ID_SPI    (13) // Serial Peripheral Interface
#define AT91C_ID_SSC0   (14) // Serial Synchronous Controller 0
#define AT91C_ID_SSC1   (15) // Serial Synchronous Controller 1
#define AT91C_ID_SSC2   (16) // Serial Synchronous Controller 2
#define AT91C_ID_TC0    (17) // Timer Counter 0
#define AT91C_ID_TC1    (18) // Timer Counter 1
#define AT91C_ID_TC2    (19) // Timer Counter 2
#define AT91C_ID_TC3    (20) // Timer Counter 3
#define AT91C_ID_TC4    (21) // Timer Counter 4
#define AT91C_ID_TC5    (22) // Timer Counter 5
#define AT91C_ID_UHP    (23) // USB Host port
#define AT91C_ID_EMAC   (24) // Ethernet MAC
#define AT91C_ID_IRQ0   (25) // Advanced Interrupt Controller (IRQ0)
#define AT91C_ID_IRQ1   (26) // Advanced Interrupt Controller (IRQ1)
#define AT91C_ID_IRQ2   (27) // Advanced Interrupt Controller (IRQ2)
#define AT91C_ID_IRQ3   (28) // Advanced Interrupt Controller (IRQ3)
#define AT91C_ID_IRQ4   (29) // Advanced Interrupt Controller (IRQ4)
#define AT91C_ID_IRQ5   (30) // Advanced Interrupt Controller (IRQ5)
#define AT91C_ID_IRQ6   (31) // Advanced Interrupt Controller (IRQ6)


// *****************************************************************************
//               BASE ADDRESS DEFINITIONS FOR AT91RM9200
// *****************************************************************************
#define AT91C_BASE_SYS		(0xFFFFF000) // (SYS) Base Address
#define AT91C_BASE_PDC_SPI	(0xFFFE0100) // (PDC_SPI) Base Address
#define AT91C_BASE_SPI		(0xFFFE0000) // (SPI) Base Address
#define AT91C_BASE_PDC_SSC2	(0xFFFD8100) // (PDC_SSC2) Base Address
#define AT91C_BASE_SSC2		(0xFFFD8000) // (SSC2) Base Address
#define AT91C_BASE_PDC_SSC1	(0xFFFD4100) // (PDC_SSC1) Base Address
#define AT91C_BASE_SSC1		(0xFFFD4000) // (SSC1) Base Address
#define AT91C_BASE_PDC_SSC0	(0xFFFD0100) // (PDC_SSC0) Base Address
#define AT91C_BASE_SSC0		(0xFFFD0000) // (SSC0) Base Address
#define AT91C_BASE_PDC_US3	(0xFFFCC100) // (PDC_US3) Base Address
#define AT91C_BASE_US3		(0xFFFCC000) // (US3) Base Address
#define AT91C_BASE_PDC_US2	(0xFFFC8100) // (PDC_US2) Base Address
#define AT91C_BASE_US2		(0xFFFC8000) // (US2) Base Address
#define AT91C_BASE_PDC_US1	(0xFFFC4100) // (PDC_US1) Base Address
#define AT91C_BASE_US1		(0xFFFC4000) // (US1) Base Address
#define AT91C_BASE_PDC_US0	(0xFFFC0100) // (PDC_US0) Base Address
#define AT91C_BASE_US0		(0xFFFC0000) // (US0) Base Address
#define AT91C_BASE_EMAC		(0xFFFBC000) // (EMAC) Base Address
#define AT91C_BASE_PDC_MCI	(0xFFFB4100) // (PDC_MCI) Base Address
#define AT91C_BASE_TWI		(0xFFFB8000) // (TWI) Base Address
#define AT91C_BASE_MCI		(0xFFFB4000) // (MCI) Base Address
#define AT91C_BASE_UDP		(0xFFFB0000) // (UDP) Base Address
#define AT91C_BASE_TC5		(0xFFFA4080) // (TC5) Base Address
#define AT91C_BASE_TC4		(0xFFFA4040) // (TC4) Base Address
#define AT91C_BASE_TC3		(0xFFFA4000) // (TC3) Base Address
#define AT91C_BASE_TCB1		(0xFFFA4000) // (TCB1) Base Address
#define AT91C_BASE_TC2		(0xFFFA0080) // (TC2) Base Address
#define AT91C_BASE_TC1		(0xFFFA0040) // (TC1) Base Address
#define AT91C_BASE_TC0		(0xFFFA0000) // (TC0) Base Address
#define AT91C_BASE_TCB0		(0xFFFA0000) // (TCB0) Base Address

#define AT91C_BASE_CS5		(0x60000000) // 10M eth Base Address
//#define AT91C_BASE_SMC2      (0xFFFFFF70) // (SMC2) Base Address
//#define AT91C_BASE_AIC		(0xFFFFF000) // 10M eth Base Address



// *****************************************************************************
//               PIO DEFINITIONS FOR AT91RM9200
// *****************************************************************************
#define AT91C_PIO_PA0		(1 <<  0)
#define AT91C_PA0_MISO		(AT91C_PIO_PA0) //  SPI Master In Slave
#define AT91C_PA0_PCK3		(AT91C_PIO_PA0) //  PMC Programmable Clock Output 3
#define AT91C_PIO_PA1		(1 <<  1)
#define AT91C_PA1_MOSI		(AT91C_PIO_PA1) //  SPI Master Out Slave
#define AT91C_PA1_PCK0		(AT91C_PIO_PA1) //  PMC Programmable Clock Output 0
#define AT91C_PIO_PA2		(1 <<  2)
#define AT91C_PA2_SPCK		(AT91C_PIO_PA2) //  SPI Serial Clock
#define AT91C_PA2_IRQ4		(AT91C_PIO_PA2) //  AIC Interrupt Input 4
#define AT91C_PIO_PA3		(1 <<  3)
#define AT91C_PA3_NPCS0		(AT91C_PIO_PA3) //  SPI Peripheral Chip Select 0
#define AT91C_PA3_IRQ5		(AT91C_PIO_PA3) //  AIC Interrupt Input 5
#define AT91C_PIO_PA4		(1 <<  4)
#define AT91C_PA4_NPCS1		(AT91C_PIO_PA4) //  SPI Peripheral Chip Select 1
#define AT91C_PA4_PCK1		(AT91C_PIO_PA4) //  PMC Programmable Clock Output 1
#define AT91C_PIO_PA5		(1 <<  5)
#define AT91C_PA5_NPCS2		(AT91C_PIO_PA5) //  SPI Peripheral Chip Select 2
#define AT91C_PA5_TXD3		(AT91C_PIO_PA5) //  USART 3 Transmit Data
#define AT91C_PIO_PA6		(1 <<  6)
#define AT91C_PA6_NPCS3		(AT91C_PIO_PA6) //  SPI Peripheral Chip Select 3
#define AT91C_PA6_RXD3		(AT91C_PIO_PA6) //  USART 3 Receive Data
#define AT91C_PIO_PA7		(1 <<  7)
#define AT91C_PA7_ETXCK_EREFCK	(AT91C_PIO_PA7) //  Ethernet MAC Transmit Clock/Reference Clock
#define AT91C_PA7_PCK2		(AT91C_PIO_PA7) //  PMC Programmable Clock 2
#define AT91C_PIO_PA8		(1 <<  8)
#define AT91C_PA8_ETXEN		(AT91C_PIO_PA8) //  Ethernet MAC Transmit Enable
#define AT91C_PA8_MCCDB		(AT91C_PIO_PA8) //  Multimedia Card B Command
#define AT91C_PIO_PA9		(1 <<  9)
#define AT91C_PA9_ETX0		(AT91C_PIO_PA9) //  Ethernet MAC Transmit Data 0
#define AT91C_PA9_MCDB0		(AT91C_PIO_PA9) //  Multimedia Card B Data 0
#define AT91C_PIO_PA10		(1 << 10)
#define AT91C_PA10_ETX1		(AT91C_PIO_PA10) //  Ethernet MAC Transmit Data 1
#define AT91C_PA10_MCDB1	(AT91C_PIO_PA10) //  Multimedia Card B Data 1
#define AT91C_PIO_PA11		(1 << 11)
#define AT91C_PA11_ECRS_ECRSDV	(AT91C_PIO_PA11) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
#define AT91C_PA11_MCDB2	(AT91C_PIO_PA11) //  Multimedia Card B Data 2
#define AT91C_PIO_PA12		(1 << 12)
#define AT91C_PA12_ERX0		(AT91C_PIO_PA12) //  Ethernet MAC Receive Data 0
#define AT91C_PA12_MCDB3	(AT91C_PIO_PA12) //  Multimedia Card B Data 3
#define AT91C_PIO_PA13 		(1 << 13)
#define AT91C_PA13_ERX1		(AT91C_PIO_PA13) //  Ethernet MAC Receive Data 1
#define AT91C_PA13_TCLK0	(AT91C_PIO_PA13) //  Timer Counter 0 external clock input
#define AT91C_PIO_PA14		(1 << 14)
#define AT91C_PA14_ERXER	(AT91C_PIO_PA14) //  Ethernet MAC Receive Error
#define AT91C_PA14_TCLK1	(AT91C_PIO_PA14) //  Timer Counter 1 external clock input
#define AT91C_PIO_PA15		(1 << 15)
#define AT91C_PA15_EMDC		(AT91C_PIO_PA15) //  Ethernet MAC Management Data Clock
#define AT91C_PA15_TCLK2	(AT91C_PIO_PA15) //  Timer Counter 2 external clock input
#define AT91C_PIO_PA16		(1 << 16)
#define AT91C_PA16_EMDIO	(AT91C_PIO_PA16) //  Ethernet MAC Management Data Input/Output
#define AT91C_PA16_IRQ6		(AT91C_PIO_PA16) //  AIC Interrupt input 6
#define AT91C_PIO_PA17		(1 << 17)
#define AT91C_PA17_TXD0		(AT91C_PIO_PA17) //  USART 0 Transmit Data
#define AT91C_PA17_TIOA0	(AT91C_PIO_PA17) //  Timer Counter 0 Multipurpose Timer I/O Pin A
#define AT91C_PIO_PA18		(1 << 18)
#define AT91C_PA18_RXD0		(AT91C_PIO_PA18) //  USART 0 Receive Data
#define AT91C_PA18_TIOB0	(AT91C_PIO_PA18) //  Timer Counter 0 Multipurpose Timer I/O Pin B
#define AT91C_PIO_PA19		(1 << 19)
#define AT91C_PA19_SCK0		(AT91C_PIO_PA19) //  USART 0 Serial Clock
#define AT91C_PA19_TIOA1	(AT91C_PIO_PA19) //  Timer Counter 1 Multipurpose Timer I/O Pin A
#define AT91C_PIO_PA20		(1 << 20)
#define AT91C_PA20_CTS0		(AT91C_PIO_PA20) //  USART 0 Clear To Send
#define AT91C_PA20_TIOB1	(AT91C_PIO_PA20) //  Timer Counter 1 Multipurpose Timer I/O Pin B
#define AT91C_PIO_PA21		(1 << 21)
#define AT91C_PA21_RTS0		(AT91C_PIO_PA21) //  USART 0 Ready To Send
#define AT91C_PA21_TIOA2	(AT91C_PIO_PA21) //  Timer Counter 2 Multipurpose Timer I/O Pin A
#define AT91C_PIO_PA22		(1 << 22)
#define AT91C_PA22_RXD2		(AT91C_PIO_PA22) //  USART 2 Receive Data
#define AT91C_PA22_TIOB2	(AT91C_PIO_PA22) //  Timer Counter 2 Multipurpose Timer I/O Pin B
#define AT91C_PIO_PA23		(1 << 23)
#define AT91C_PA23_TXD2		(AT91C_PIO_PA23) //  USART 2 Transmit Data
#define AT91C_PA23_IRQ3		(AT91C_PIO_PA23) //  Interrupt input 3
#define AT91C_PIO_PA24		(1 << 24)
#define AT91C_PA24_SCK2		(AT91C_PIO_PA24) //  USART2 Serial Clock
#define AT91C_PA24_PCK1		(AT91C_PIO_PA24) //  PMC Programmable Clock Output 1
#define AT91C_PIO_PA25		(1 << 25)
#define AT91C_PA25_TWD		(AT91C_PIO_PA25) //  TWI Two-wire Serial Data
#define AT91C_PA25_IRQ2		(AT91C_PIO_PA25) //  Interrupt input 2
#define AT91C_PIO_PA26		(1 << 26)
#define AT91C_PA26_TWCK		(AT91C_PIO_PA26) //  TWI Two-wire Serial Clock
#define AT91C_PA26_IRQ1		(AT91C_PIO_PA26) //  Interrupt input 1
#define AT91C_PIO_PA27		(1 << 27)
#define AT91C_PA27_MCCK		(AT91C_PIO_PA27) //  Multimedia Card Clock
#define AT91C_PA27_TCLK3	(AT91C_PIO_PA27) //  Timer Counter 3 External Clock Input
#define AT91C_PIO_PA28		(1 << 28)
#define AT91C_PA28_MCCDA	(AT91C_PIO_PA28) //  Multimedia Card A Command
#define AT91C_PA28_TCLK4	(AT91C_PIO_PA28) //  Timer Counter 4 external Clock Input
#define AT91C_PIO_PA29		(1 << 29)
#define AT91C_PA29_MCDA0	(AT91C_PIO_PA29) //  Multimedia Card A Data 0
#define AT91C_PA29_TCLK5	(AT91C_PIO_PA29) //  Timer Counter 5 external clock input
#define AT91C_PIO_PA30		(1 << 30)
#define AT91C_PA30_DRXD		(AT91C_PIO_PA30) //  DBGU Debug Receive Data
#define AT91C_PA30_CTS2		(AT91C_PIO_PA30) //  USART 2 Clear To Send
#define AT91C_PIO_PA31		(1 << 31)
#define AT91C_PA31_DTXD		(AT91C_PIO_PA31) //  DBGU Debug Transmit Data
#define AT91C_PA31_RTS2		(AT91C_PIO_PA31) //  USART 2 Ready To Send

#define AT91C_PIO_PB0		(1 <<  0)
#define AT91C_PB0_TF0		(AT91C_PIO_PB0) //  SSC Transmit Frame Sync 0
#define AT91C_PB0_RTS3		(AT91C_PIO_PB0) //  USART 3 Ready To Send
#define AT91C_PIO_PB1		(1 <<  1)
#define AT91C_PB1_TK0		(AT91C_PIO_PB1) //  SSC Transmit Clock 0
#define AT91C_PB1_CTS3		(AT91C_PIO_PB1) //  USART 3 Clear To Send
#define AT91C_PIO_PB2		(1 <<  2)
#define AT91C_PB2_TD0		(AT91C_PIO_PB2) //  SSC Transmit data
#define AT91C_PB2_SCK3		(AT91C_PIO_PB2) //  USART 3 Serial Clock