start.s

uboot针对三星公司的s3c2410（arm920T核）的初始化源代码。

/*
 *  armboot - Startup Code for ARM920 CPU-core
 *
 *  Copyright (c) 2001	Marius Gr鰃er <[e-mail]>
 *  Copyright (c) 2002	Alex Z黳ke <[e-mail]>
 *  Copyright (c) 2002	Gary Jennejohn <[e-mail]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 */


#include <config.h>
#include <version.h>

#include "memory.h"
#include <../board/smdk2440/memsetup.S>

#undef CONFIG_DEBUG_LL

/*
 *************************************************************************
 *
 * Jump vector table as in table 3.1 in [1]
 *
 *************************************************************************
 */


.globl _start
_start:	b       reset
	ldr	pc, _undefined_instruction
	ldr	pc, _software_interrupt
	ldr	pc, _prefetch_abort
	ldr	pc, _data_abort
	ldr	pc, _not_used
	ldr	pc, _irq
	ldr	pc, _fiq
#ifdef CONFIG_PM	
	b		sleep_setting
#endif
_undefined_instruction:	.word undefined_instruction
_software_interrupt:	.word software_interrupt
_prefetch_abort:	.word prefetch_abort
_data_abort:		.word data_abort
_not_used:		.word not_used
_irq:			.word irq
_fiq:			.word fiq

	.balignl 16,0xdeadbeef


/*
 *************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * relocate armboot to ram
 * setup stack
 * jump to second stage
 *
 *************************************************************************
 */

_TEXT_BASE:
	.word	TEXT_BASE

.globl _armboot_start
_armboot_start:
	.word _start

/*
 * Note: _armboot_end_data and _armboot_end are defined
 * by the (board-dependent) linker script.
 * _armboot_end_data is the first usable FLASH address after armboot
 */
.globl _armboot_end_data
_armboot_end_data:
	.word armboot_end_data
.globl _armboot_end
_armboot_end:
	.word armboot_end

/*
 * _armboot_real_end is the first usable RAM address behind armboot
 * and the various stacks
 */
.globl _armboot_real_end
_armboot_real_end:
	.word 0x0badc0de

/*
 * These are defined in the board-specific linker script.
 */
.globl _bss_start
_bss_start:
        .word __bss_start

.globl _bss_end
_bss_end:
        .word _end


/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de

#ifdef CONFIG_S3C2440A_SMDK
@ Processor clock values
#if (CONFIG_SYS_CLK_FREQ ==  12000000)
#define MDIV_406               195
#define PDIV_406               4
#define SDIV_406               1

#define MDIV_405               127
#define PDIV_405               2
#define SDIV_405               1

#define MDIV_96                56
#define PDIV_96                2
#define SDIV_96                1

#define MDIV_48                56
#define PDIV_48                2
#define SDIV_48                2

#define CLKDIVN_136            0xf  /* UCLK = UPLL/2 */
#define CLKDIVN_148            0x5  /* UCLK = UPLL/2 */

#define vUPLLCON_NOW_USER       ((MDIV_48 << 12) | (PDIV_48 << 4) | (SDIV_48))
#define vMPLLCON_NOW_USER       ((MDIV_406 << 12) | (PDIV_406 << 4) | (SDIV_406))
#define CLKDIVN_VAL		CLKDIVN_148

#else /* SYS_CLK_FREQ == 16.9344Mhz */ 
#define MDIV_533                118
#define PDIV_533                2
#define SDIV_533                1
/* In 533, you must use CLKDIVN_148 instead of CLKDIVN_136 */

#define MDIV_406                110
#define PDIV_406                3
#define SDIV_406                1
#define CLKDIVN_136             0x5 /* UCLK = UPLL/2 */
#define vREFRESH_406            992
#define MDIV_96                 60
#define PDIV_96                 4
#define SDIV_96                 1
#define vMPLLCON_NOW_USER       ((MDIV_406 << 12) | (PDIV_406 << 4) | (SDIV_406))
#define vUPLLCON_NOW_USER       ((MDIV_96 << 12) | (PDIV_96 << 4) | (SDIV_96))
#define CLKDIVN_VAL		CLKDIVN_136
#endif

#define pWTCON          0x53000000
#define SRCPND		0x4A000000
#define INTMSK          0x4A000008
#define INTSUBMSK       0x4A00001C
#define LOCKTIME 	0x4C000000
#define MPLLCON		0x4C000004
#define UPLLCON 	0x4C000008
#define CLKCON		0x4C00000C
#define CLKSLOW		0x4C000010
#define CLKDIVN         0x4C000014
#define CAMDIVN 	0x4C000018
#define GPFCON		0x56000050
#define GPFDAT		0x56000054
#define GPFUP		0x56000058

#define GPCCON		0x56000020
#define GPCDAT		0x56000024
#define GPCUP		0x56000028


/*
 * the actual reset code
 */

reset:
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0xd3
	msr	cpsr,r0

	ldr     r0, =pWTCON
	mov     r1, #0x0
	str     r1, [r0]

	/*
	 * mask all IRQs by setting all bits in the INTMR - default
	 */
	mov	r1, #0xffffffff
	ldr	r0, =INTMSK
	str	r1, [r0]
	ldr r2, =0x7ff
	ldr r0, =INTSUBMSK
	str r2, [r0]
	
        @ initialize system clocks
	ldr	r0, =LOCKTIME
	ldr     r1, =0xffffff 
	str     r1, [r0]

        /* FCLK:HCLK:PCLK */
	ldr	r0, =CAMDIVN
	mov	r1, #0
	str	r1, [r0]
        ldr     r0, =CLKDIVN
        ldr     r1, =CLKDIVN_VAL
        str     r1, [r0]

        mrc     p15, 0, r1, c1, c0, 0           @ read ctrl register
        orr     r1, r1, #0xc0000000             @ Asynchronous
        mcr     p15, 0, r1, c1, c0, 0           @ write ctrl register

	/* UPLL setup */
        ldr     r0, =UPLLCON
        ldr	r1, upll_value_USER
        str     r1, [r0]

	nop
	nop
	nop
	nop	
	nop		@ wait until upll has the effect
	nop
	nop	
	nop	
        /* PLL setup */
	ldr     r0, =MPLLCON
	ldr	r1, mpll_value_USER
	str     r1, [r0]

	/*
	 * we do sys-critical inits only at reboot,
	 * not when booting from ram!
	 */
#ifdef CONFIG_INIT_CRITICAL
	bl	cpu_init_crit
#endif

#ifdef CONFIG_PM
	@ Check if this is a wake-up from sleep
	ldr r1, PMST_ADDR
	ldr r0, [r1]
	tst r0, #0x2 @ PMST_SMR
	bne WakeupStart
#endif



#ifndef CONFIG_S3C2440A_JTAG_BOOT

#ifdef CONFIG_S3C2440A_NAND_BOOT
	bl      copy_myself
#else
relocate:
	/*
	 * relocate armboot to RAM
	 */
	adr	r0, _start		/* r0 <- current position of code */
	ldr	r2, _armboot_start
	ldr	r3, _armboot_end
	sub	r2, r3, r2		/* r2 <- size of armboot */
	ldr	r1, _TEXT_BASE		/* r1 <- destination address */
	add	r2, r0, r2		/* r2 <- source end address */

	/*
	 * r0 = source address
	 * r1 = target address
	 * r2 = source end address
	 */
copy_loop:
	ldmia	r0!, {r3-r10}
	stmia	r1!, {r3-r10}
	cmp	r0, r2
	ble	copy_loop
#endif
#endif

clear_bss:
        ldr     r0, _bss_start          /* find start of bss segment        */
        add     r0, r0, #4              /* start at first byte of bss       */
        ldr     r1, _bss_end            /* stop here                        */
        mov     r2, #0x00000000         /* clear                            */

clbss_l:str     r2, [r0]                /* clear loop...                    */
        add     r0, r0, #4
        cmp     r0, r1
        bne     clbss_l

	/* set up the stack */
	ldr	r0, _armboot_end
	add	r0, r0, #CONFIG_STACKSIZE
	sub	sp, r0, #12		/* leave 3 words for abort-stack */

	ldr	pc, _start_armboot

_start_armboot:	.word start_armboot



.align 4
mpll_value_USER:
        .long   vMPLLCON_NOW_USER

upll_value_USER:
        .long   vUPLLCON_NOW_USER
#endif


/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */

cpu_init_crit:
	/*
	 * flush v4 I/D caches
	 */
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */

	/*
	 * disable MMU stuff and caches
	 */
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
	mcr	p15, 0, r0, c1, c0, 0


	/*
	 * before relocating, we have to setup RAM timing
	 * because memory timing is board-dependend, you will
	 * find a memsetup.S in your board directory.
	 */
	mov	ip, lr
	bl	memsetup