📄 os_cpu_a.lst
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221 00000084 ; TICK HANDLE
R
ARM Macro Assembler Page 6
222 00000084 ;
223 00000084 ; Description:
224 00000084 ; This handles all the Timer0(INT_TIMER0) interrupt
which is used to generate the uC/OS-II tick.
225 00000084 ;*******************************************************
**************************************************/
226 00000084
227 00000084 OSTickISR
228 00000084 E1A0500E MOV R5,LR
229 00000088 E3A01001 MOV R1, #1
230 0000008C E1A01501 MOV R1, R1, LSL #10 ; Timer0 Source
Pending Reg.
231 00000090 E3A0044A LDR R0, =SRCPND
232 00000094 E5902000 LDR R2, [R0]
233 00000098 E1811002 ORR R1, R1,R2
234 0000009C E5801000 STR R1, [R0]
235 000000A0
236 000000A0 E59F00F0 LDR R0, =INTPND
237 000000A4 E5901000 LDR R1, [R0]
238 000000A8 E5801000 STR R1, [R0]
239 000000AC
240 000000AC ;-------------------------------------------------------
---------------------------
241 000000AC ; OSTimeTick();
242 000000AC ;-------------------------------------------------------
---------------------------
243 000000AC EBFFFFFE BL OSTimeTick
244 000000B0 ; BL OSIntExit
245 000000B0
246 000000B0
247 000000B0 ;MOV PC, R5 ; Return
248 000000B0 E12FFF15 BX R5
249 000000B4 ;*******************************************************
**************************************************
250 000000B4 ; PERFORM A CONTEXT SWITC
H (From an ISR)
251 000000B4 ; void OSIntCtxSw
(void)
252 000000B4 ;
253 000000B4 ; Description: 1) This code performs a context switch if
a higher priority task has been made ready-to-run
254 000000B4 ; during an ISR.
255 000000B4 ;
256 000000B4 ; 2) The stack frame of the task to suspend
looks as follows:
257 000000B4 ;
258 000000B4 ; PC (High memory)
259 000000B4 ; LR(R
14)
260 000000B4 ; R12
261 000000B4 ; R11
262 000000B4 ; R10
263 000000B4 ; R9
264 000000B4 ; R8
265 000000B4 ; R7
266 000000B4 ; R6
267 000000B4 ; R5
268 000000B4 ; R4
269 000000B4 ; R3
ARM Macro Assembler Page 7
270 000000B4 ; R2
271 000000B4 ; R1
272 000000B4 ; R0
273 000000B4 ;
274 000000B4 ; OSTCBCur->OSTCBStkPtr ----> CPSR (Low memory
)
275 000000B4 ;
276 000000B4 ;
277 000000B4 ; 3) The stack frame of the task to resume
looks as follows:
278 000000B4 ;
279 000000B4 ; PC (High memory)
280 000000B4 ; LR(R
14)
281 000000B4 ; R12
282 000000B4 ; R11
283 000000B4 ; R10
284 000000B4 ; R9
285 000000B4 ; R8
286 000000B4 ; R7
287 000000B4 ; R6
288 000000B4 ; R5
289 000000B4 ; R4
290 000000B4 ; R3
291 000000B4 ; R2
292 000000B4 ; R1
293 000000B4 ; R0
294 000000B4 ; OSTCBHighRdy->OSTCBStkPtr ----> CPSR (Low mem
ory)
295 000000B4 ;*******************************************************
**************************************************/
296 000000B4 OSIntCtxSw
297 000000B4 ;-------------------------------------------------------
---------------------------
298 000000B4 ; Call OSTaskSwHook();
299 000000B4 ;-------------------------------------------------------
---------------------------
300 000000B4 EBFFFFFE BL OSTaskSwHook
301 000000B8
302 000000B8 ;-------------------------------------------------------
---------------------------
303 000000B8 ; OSTCBCur = OSTCBHighRdy;
304 000000B8 ;-------------------------------------------------------
---------------------------
305 000000B8 E59F00C8 LDR R0, =OSTCBHighRdy
306 000000BC E59F10C8 LDR R1, =OSTCBCur
307 000000C0 E5900000 LDR R0, [R0]
308 000000C4 E5810000 STR R0, [R1]
309 000000C8
310 000000C8 ;-------------------------------------------------------
---------------------------
311 000000C8 ; OSPrioCur = OSPrioHighRdy;
312 000000C8 ;-------------------------------------------------------
---------------------------
313 000000C8 E59F00C0 LDR R0, =OSPrioHighRdy
314 000000CC E59F10C0 LDR R1, =OSPrioCur
315 000000D0 E5D00000 LDRB R0, [R0]
316 000000D4 E5C10000 STRB R0, [R1]
317 000000D8
ARM Macro Assembler Page 8
318 000000D8 ;-------------------------------------------------------
---------------------------
319 000000D8 ; SP = OSTCBHighRdy->OSTCBStkPtr;
320 000000D8 ;-------------------------------------------------------
---------------------------
321 000000D8 E59F00A8 LDR R0, =OSTCBHighRdy
322 000000DC E5900000 LDR R0, [R0]
323 000000E0 E590D000 LDR SP, [R0]
324 000000E4
325 000000E4 ;-------------------------------------------------------
---------------------------
326 000000E4 ; Restore New Task context
327 000000E4 ;-------------------------------------------------------
---------------------------
328 000000E4 E8BD0001 LDMFD SP!, {R0} ;POP CPSR
329 000000E8 E16FF000 MSR SPSR_cxsf, R0
330 000000EC E8FDDFFF LDMFD SP!, {R0-R12, LR, PC}^
331 000000F0
332 000000F0
333 000000F0
334 000000F0 OS_CPU_IRQ_ISR
335 000000F0
336 000000F0 E92D000E STMFD SP!, {R1-R3} ; We will use R1-R
3 as temporary regi
sters
337 000000F4 ;-------------------------------------------------------
---------------------
338 000000F4 ; R1--SP
339 000000F4 ; R2--PC
340 000000F4 ; R3--SPSR
341 000000F4 ;-------------------------------------------------------
-----------------
342 000000F4 E1A0100D MOV R1, SP
343 000000F8 E28DD00C ADD SP, SP, #12 ;Adjust IRQ stack p
ointer
344 000000FC E24E2004 SUB R2, LR, #4 ;Adjust PC for retu
rn address to task
345 00000100
346 00000100 E14F3000 MRS R3, SPSR ; Copy SPSR (Task C
PSR)
347 00000104
348 00000104
349 00000104
350 00000104 E32FF0D3 MSR CPSR_cxsf, #SVCMODE|NOINT
;Change to SVC mode
351 00000108
352 00000108 ; SAVE TASK''S CONTEXT ONTO OLD TASK''S STACK
353 00000108
354 00000108 E92D0004 STMFD SP!, {R2} ; Push task''s PC
355 0000010C E92D5FF0 STMFD SP!, {R4-R12, LR} ; Push task''
s LR,R12-R4
356 00000110
357 00000110 E8B10070 LDMFD R1!, {R4-R6} ; Load Task''s R1-
R3 from IRQ stack
358 00000114 E92D0070 STMFD SP!, {R4-R6} ; Push Task''s R1-
R3 to SVC stack
359 00000118 E92D0001 STMFD SP!, {R0} ; Push Task''s R0 t
o SVC stack
ARM Macro Assembler Page 9
360 0000011C
361 0000011C E92D0008 STMFD SP!, {R3} ; Push task''s CPSR
362 00000120
363 00000120 E59F0074 LDR R0,=OSIntNesting
;OSIntNesting++
364 00000124 E5D01000 LDRB R1,[R0]
365 00000128 E2811001 ADD R1,R1,#1
366 0000012C E5C01000 STRB R1,[R0]
367 00000130
368 00000130 E3510001 CMP R1,#1 ;if(OSIntNesting==1
){
369 00000134 1A000002 BNE %F1
370 00000138
371 00000138 E59F404C LDR R4,=OSTCBCur ;OSTCBHighRdy->OST
CBStkPtr=SP;
372 0000013C E5945000 LDR R5,[R4]
373 00000140 E585D000 STR SP,[R5] ;}
374 00000144
375 00000144 1
376 00000144 E321F0D2 MSR CPSR_c,#IRQMODE|NOINT ;Change t
o IRQ mode to use I
RQ stack to handle
interrupt
377 00000148 E59FE050 LDR LR,=L_IRQ_Return
378 0000014C
379 0000014C E59FF050 LDR PC,=IRQ_Dispatch
380 00000150
381 00000150
382 00000150 L_IRQ_Return
383 00000150 E321F0D3 MSR CPSR_c,#SVCMODE|NOINT
;Change to SVC mode
384 00000154 EBFFFFFE BL OSIntExit ;Call OSIntExit
385 00000158
386 00000158 E8BD0010 LDMFD SP!,{R4} ;POP the task''s CP
SR
387 0000015C E16FF004 MSR SPSR_cxsf,R4
388 00000160 E8FDDFFF LDMFD SP!,{R0-R12,LR,PC}^ ;POP new Ta
sk''s context
389 00000164
390 00000164 ;IRQIsrVect DCD HandleEINT0
391 00000164
392 00000164 ;*******************************************************
**************************************************
393 00000164 ; CRITICAL SECTION MET
HOD 3 FUNCTIONS
394 00000164 ;
395 00000164 ; Description: Disable/Enable interrupts by preserving t
he state of interrupts. Generally speaking you
396 00000164 ; would store the state of the interrupt di
sable flag in the local variable 'cpu_sr' and then
397 00000164 ; disable interrupts. 'cpu_sr' is allocate
d in all of uC/OS-II''s functions that need to
398 00000164 ; disable interrupts. You would restore th
e interrupt disable state by copying back 'cpu_sr'
399 00000164 ; into the CPU''s status register.
400 00000164 ;
401 00000164 ; Prototypes : OS_CPU_SR OSCPUSaveSR(void);
ARM Macro Assembler Page 10
402 00000164 ; void OSCPURestoreSR(OS_CPU_SR cpu_s
r);
403 00000164 ;
404 00000164 ;
405 00000164 ; Note(s) : 1) These functions are used in general li
ke this:
406 00000164 ;
407 00000164 ; void Task (void *p_arg)
408 00000164 ; {
409 00000164 ; #if OS_CRITICAL_METHOD == 3 /
* Allocate storage for CPU status register */
410 00000164 ; OS_CPU_SR cpu_sr;
411 00000164 ; #endif
412 00000164 ;
413 00000164 ; :
414 00000164 ; :
415 00000164 ; OS_ENTER_CRITICAL(); /
* cpu_sr = OSCPUSaveSR(); */
416 00000164 ; :
417 00000164 ; :
418 00000164 ; OS_EXIT_CRITICAL(); /
* OSCPURestoreSR(cpu_sr); */
419 00000164 ; :
420 00000164 ; :
421 00000164 ; }
422 00000164 ;
423 00000164 ; 2) OSCPUSaveSR() is implemented as recomm
ended by Atmel''s application note:
424 00000164 ;
425 00000164 ; "Disabling Interrupts at Processor
Level"
426 00000164 ;*******************************************************
**************************************************
427 00000164 OSCPUSaveSR
428 00000164 E10F0000 mrs r0, cpsr
429 00000168 E92D0001 stmfd sp!, {r0}
430 0000016C E38000C0 orr r0, r0, #0xc0 ;关中断
431 00000170 E121F000 msr cpsr_c, r0
432 00000174 E12FFF1E bx lr
433 00000178 OSCPURestoreSR
434 00000178 E8BD0001 ldmfd sp!, {r0}
435 0000017C E12FF000 msr cpsr_cxsf, r0
436 00000180 E12FFF1E BX LR
437 00000184 END
00000000
00000000
00000000
00000000
00000000
4A000010
00000000
00000000
00000000
Command Line: --debug --xref --cpu=ARM920T --apcs=interwork --depend=..\out\Os_
cpu_a.d -o..\out\Os_cpu_a.o -Id:\Keil\ARM\INC -Id:\Keil\ARM\INC\Samsung --list=
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