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📄 bank_init.lst

📁 ucos_ii在mini2440上的移植KEIL编译环境
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                       NFMECCD1
                               EQU              0x4E000018
  104 00000000 4E00001C 
                       NFSECCD EQU              0x4E00001C  ;NAND Flash ECC for
                                                             Spare Area
  105 00000000 4E000020 
                       NFSTAT  EQU              0x4E000020  ;NAND Flash operati
                                                            on status
  106 00000000 4E000024 
                       NFESTAT0
                               EQU              0x4E000024
  107 00000000 4E000028 
                       NFESTAT1
                               EQU              0x4E000028
  108 00000000 4E00002C 
                       NFMECC0 EQU              0x4E00002C
  109 00000000 4E000030 
                       NFMECC1 EQU              0x4E000030
  110 00000000 4E000034 
                       NFSECC  EQU              0x4E000034
  111 00000000 4E000038 
                       NFSBLK  EQU              0x4E000038  ;NAND Flash Start b
                                                            lock address
  112 00000000 4E00003C 
                       NFEBLK  EQU              0x4E00003C  ;NAND Flash End blo
                                                            ck address
  113 00000000         
  114 00000000                 END
    8 00000000                 EXPORT           InitBank
    9 00000000         
   10 00000000         
   11 00000000         
   12 00000000         ;BWSCON
   13 00000000 00000000 
                       DW8     EQU              (0X0)
   14 00000000 00000001 
                       DW16    EQU              (0X1)
   15 00000000 00000002 
                       DW32    EQU              (0X2)
   16 00000000 00000004 
                       WAIT    EQU              (0X1 << 2)
   17 00000000 00000008 
                       UBLB    EQU              (0X1 << 3)
   18 00000000         
   19 00000000 00000002 
                       B0_BWS  EQU              (DW16 << 1)
   20 00000000 00000020 
                       B1_BWS  EQU              (DW32 << 4)



ARM Macro Assembler    Page 6 


   21 00000000 00000100 
                       B2_BWS  EQU              (DW16 << 8)
   22 00000000 00001000 
                       B3_BWS  EQU              (DW16 << 12)
   23 00000000 00010000 
                       B4_BWS  EQU              (DW16 << 16)
   24 00000000 00100000 
                       B5_BWS  EQU              (DW16 << 20)
   25 00000000 02000000 
                       B6_BWS  EQU              (DW32 << 24)
   26 00000000 20000000 
                       B7_BWS  EQU              (DW32 << 28)
   27 00000000         
   28 00000000         ;BANK0配置参数
   29 00000000 00000000 
                       B0_Tacs EQU              (0X0 << 13)
   30 00000000 00000000 
                       B0_Tcos EQU              (0X0 << 11)
   31 00000000 00000700 
                       B0_Tacc EQU              (0X7 << 8)
   32 00000000 00000000 
                       B0_tcoh EQU              (0X0 << 6)
   33 00000000 00000000 
                       B0_tah  EQU              (0X0 << 4)
   34 00000000 00000000 
                       B0_tacp EQU              (0X0 << 2)
   35 00000000 00000000 
                       B0_tPMC EQU              (0X0 << 0)
   36 00000000         
   37 00000000         ;BANK1配置参数
   38 00000000 00000000 
                       B1_Tacs EQU              (0X0 << 13)
   39 00000000 00000000 
                       B1_Tcos EQU              (0X0 << 11)
   40 00000000 00000700 
                       B1_Tacc EQU              (0X7 << 8)
   41 00000000 00000000 
                       B1_tcoh EQU              (0X0 << 6)
   42 00000000 00000000 
                       B1_tah  EQU              (0X0 << 4)
   43 00000000 00000000 
                       B1_tacp EQU              (0X0 << 2)
   44 00000000 00000000 
                       B1_tPMC EQU              (0X0 << 0)
   45 00000000         
   46 00000000         ;BANK2配置参数
   47 00000000 00000000 
                       B2_Tacs EQU              (0X0 << 13)
   48 00000000 00000000 
                       B2_Tcos EQU              (0X0 << 11)
   49 00000000 00000700 
                       B2_Tacc EQU              (0X7 << 8)
   50 00000000 00000000 
                       B2_tcoh EQU              (0X0 << 6)
   51 00000000 00000000 
                       B2_tah  EQU              (0X0 << 4)
   52 00000000 00000000 
                       B2_tacp EQU              (0X0 << 2)
   53 00000000 00000000 



ARM Macro Assembler    Page 7 


                       B2_tPMC EQU              (0X0 << 0)
   54 00000000         
   55 00000000         ;BANK3配置参数
   56 00000000 00000000 
                       B3_Tacs EQU              (0X0 << 13)
   57 00000000 00000000 
                       B3_Tcos EQU              (0X0 << 11)
   58 00000000 00000700 
                       B3_Tacc EQU              (0X7 << 8)
   59 00000000 00000000 
                       B3_tcoh EQU              (0X0 << 6)
   60 00000000 00000000 
                       B3_tah  EQU              (0X0 << 4)
   61 00000000 00000000 
                       B3_tacp EQU              (0X0 << 2)
   62 00000000 00000000 
                       B3_tPMC EQU              (0X0 << 0)
   63 00000000         
   64 00000000         ;BANK4配置参数
   65 00000000 00000000 
                       B4_Tacs EQU              (0X0 << 13)
   66 00000000 00000000 
                       B4_Tcos EQU              (0X0 << 11)
   67 00000000 00000700 
                       B4_Tacc EQU              (0X7 << 8)
   68 00000000 00000000 
                       B4_tcoh EQU              (0X0 << 6)
   69 00000000 00000000 
                       B4_tah  EQU              (0X0 << 4)
   70 00000000 00000000 
                       B4_tacp EQU              (0X0 << 2)
   71 00000000 00000000 
                       B4_tPMC EQU              (0X0 << 0)
   72 00000000         
   73 00000000         ;BANK5配置参数
   74 00000000 00000000 
                       B5_Tacs EQU              (0X0 << 13)
   75 00000000 00000000 
                       B5_Tcos EQU              (0X0 << 11)
   76 00000000 00000700 
                       B5_Tacc EQU              (0X7 << 8)
   77 00000000 00000000 
                       B5_tcoh EQU              (0X0 << 6)
   78 00000000 00000000 
                       B5_tah  EQU              (0X0 << 4)
   79 00000000 00000000 
                       B5_tacp EQU              (0X0 << 2)
   80 00000000 00000000 
                       B5_tPMC EQU              (0X0 << 0)
   81 00000000         
   82 00000000         ;BANK6配置参数
   83 00000000 00018000 
                       B6_MT   EQU              (0X3 << 15)
   84 00000000 00000004 
                       B6_Trcd EQU              (0X1 << 2)
   85 00000000 00000001 
                       B6_SCAN EQU              (0X1 << 0)
   86 00000000         
   87 00000000         ;BANK7配置参数



ARM Macro Assembler    Page 8 


   88 00000000 00018000 
                       B7_MT   EQU              (0X3 << 15)
   89 00000000 00000004 
                       B7_Trcd EQU              (0X1 << 2)
   90 00000000 00000001 
                       B7_SCAN EQU              (0X1 << 0)
   91 00000000         
   92 00000000         ;REFRESH参数
   93 00000000 00800000 
                       REFEN   EQU              (0X1 << 23)
   94 00000000 00000000 
                       TREFMD  EQU              (0X0 << 22)
   95 00000000 00200000 
                       Trp     EQU              (0X2 << 20)
   96 00000000 00080000 
                       Trc     EQU              (0X2 << 18)
   97 00000000 00020000 
                       Tchr    EQU              (0X2 << 16)
   98 00000000 00000675 
                       REFCET  EQU              (1653 << 0)
   99 00000000         
  100 00000000         ;参数配置组合
  101 00000000 22111122 
                       BWSCON_VAL
                               EQU              (B0_BWS | B1_BWS | B2_BWS | B3_
BWS | B4_BWS | B5_BWS | B6_BWS | B7_BWS)
  102 00000000 00000700 
                       BANKCON0_VAL
                               EQU              (B0_Tacs | B0_Tcos | B0_Tacc | 
B0_tcoh | B0_tah | B0_tacp | B0_tPMC)
  103 00000000 00000700 
                       BANKCON1_VAL
                               EQU              (B1_Tacs | B1_Tcos | B1_Tacc | 
B1_tcoh | B1_tah | B1_tacp | B1_tPMC)
  104 00000000 00000700 
                       BANKCON2_VAL
                               EQU              (B2_Tacs | B2_Tcos | B2_Tacc | 
B2_tcoh | B2_tah | B2_tacp | B2_tPMC)
  105 00000000 00000700 
                       BANKCON3_VAL
                               EQU              (B3_Tacs | B3_Tcos | B3_Tacc | 
B3_tcoh | B3_tah | B3_tacp | B3_tPMC)
  106 00000000 00000700 
                       BANKCON4_VAL
                               EQU              (B4_Tacs | B4_Tcos | B4_Tacc | 
B4_tcoh | B4_tah | B4_tacp | B4_tPMC)
  107 00000000 00000700 
                       BANKCON5_VAL
                               EQU              (B5_Tacs | B5_Tcos | B5_Tacc | 
B5_tcoh | B5_tah | B5_tacp | B5_tPMC)
  108 00000000 00018005 
                       BANKCON6_VAL
                               EQU              (B6_MT | B6_Trcd | B6_SCAN)
  109 00000000 00018005 
                       BANKCON7_VAL
                               EQU              (B7_MT | B7_Trcd | B7_SCAN)
  110 00000000 00AA0675 
                       REFRESH_VAL
                               EQU              (REFEN| TREFMD | Trp | Trc | Tc



ARM Macro Assembler    Page 9 


hr | REFCET)
  111 00000000 00000032 
                       BANKSIZE_VAL
                               EQU              (0X32)
  112 00000000 00000030 
                       MRSRB6_VAL
                               EQU              (0X30)
  113 00000000 00000030 
                       MRSRB7_VAL
                               EQU              (0X30)
  114 00000000         
  115 00000000         ;配置bank的参数
  116 00000000         InitBank
  117 00000000         ;Set memory control registers
  118 00000000 E59F0018        LDR              R0,=L_BANK_CONF
  119 00000004 E3A01312        LDR              R1,=BWSCON  ;BWSCON Address
  120 00000008 E2802034        ADD              R2, R0, #52 ;End address of SMR
                                                            DATA
  121 0000000C         
  122 0000000C         0
  123 0000000C E4903004        LDR              R3, [R0], #4
  124 00000010 E4813004        STR              R3, [R1], #4
  125 00000014 E1520000        CMP              R2, R0
  126 00000018 1AFFFFFB        BNE              %B0
  127 0000001C         
  128 0000001C E12FFF1E        BX               LR
  129 00000020         ;声明一个文字池的开始,文字池一般放置在一个代码段的最后

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