📄 bank_init.lst
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ARM Macro Assembler Page 1
1 00000000 ;************************************
2 00000000 ;BANK参数配置
3 00000000 ;***********************************
4 00000000 AREA BANK, CODE, READONLY
5 00000000 ENTRY
6 00000000 CODE32
7 00000000 GET 2440addr.inc
1 00000000 ;=======================================================
=============
2 00000000 ; File Name : 2440addr.a
3 00000000 ; Function : S3C2440 Define Address Register (Assembly)
4 00000000 ; Date : March 27, 2002
5 00000000 ; Revision : Programming start (February 18,2002) -> SOP
6 00000000 ; Revision : 03.11.2003 ver 0.0 Attatched for 2440
7 00000000 ;=======================================================
=============
8 00000000
9 00000000 GBLL BIG_ENDIAN__
10 00000000 FALSE
BIG_ENDIAN__
SETL {FALSE}
11 00000000
12 00000000 ;=================
13 00000000 ; Memory control
14 00000000 ;=================
15 00000000 48000000
BWSCON EQU 0x48000000 ;Bus width & wait s
tatus
16 00000000 48000004
BANKCON0
EQU 0x48000004 ;Boot ROM control
17 00000000 48000008
BANKCON1
EQU 0x48000008 ;BANK1 control
18 00000000 4800000C
BANKCON2
EQU 0x4800000c ;BANK2 control
19 00000000 48000010
BANKCON3
EQU 0x48000010 ;BANK3 control
20 00000000 48000014
BANKCON4
EQU 0x48000014 ;BANK4 control
21 00000000 48000018
BANKCON5
EQU 0x48000018 ;BANK5 control
22 00000000 4800001C
BANKCON6
EQU 0x4800001c ;BANK6 control
23 00000000 48000020
BANKCON7
EQU 0x48000020 ;BANK7 control
24 00000000 48000024
REFRESH EQU 0x48000024 ;DRAM/SDRAM refresh
25 00000000 48000028
BANKSIZE
ARM Macro Assembler Page 2
EQU 0x48000028 ;Flexible Bank Size
26 00000000 4800002C
MRSRB6 EQU 0x4800002c ;Mode register set
for SDRAM Bank6
27 00000000 48000030
MRSRB7 EQU 0x48000030 ;Mode register set
for SDRAM Bank7
28 00000000
29 00000000
30 00000000 ;==========================
31 00000000 ; CLOCK & POWER MANAGEMENT
32 00000000 ;==========================
33 00000000 4C000000
LOCKTIME
EQU 0x4c000000 ;PLL lock time coun
ter
34 00000000 4C000004
MPLLCON EQU 0x4c000004 ;MPLL Control
35 00000000 4C000008
UPLLCON EQU 0x4c000008 ;UPLL Control
36 00000000 4C00000C
CLKCON EQU 0x4c00000c ;Clock generator co
ntrol
37 00000000 4C000010
CLKSLOW EQU 0x4c000010 ;Slow clock control
38 00000000 4C000014
CLKDIVN EQU 0x4c000014 ;Clock divider cont
rol
39 00000000
40 00000000
41 00000000 ;=================
42 00000000 ; INTERRUPT
43 00000000 ;=================
44 00000000 4A000000
SRCPND EQU 0x4a000000 ;Interrupt request
status
45 00000000 4A000004
INTMOD EQU 0x4a000004 ;Interrupt mode con
trol
46 00000000 4A000008
INTMSK EQU 0x4a000008 ;Interrupt mask con
trol
47 00000000 4A00000C
PRIORITY
EQU 0x4a00000c ;IRQ priority contr
ol <-- Ma
y 06, 2002 SOP
48 00000000 4A000010
INTPND EQU 0x4a000010 ;Interrupt request
status
49 00000000 4A000014
INTOFFSET
EQU 0x4a000014 ;Interruot request
source offset
50 00000000 4A000018
SUBSRCPND
EQU 0x4a000018 ;Sub source pending
ARM Macro Assembler Page 3
51 00000000 4A00001C
INTSUBMSK
EQU 0x4a00001c ;Interrupt sub mask
52 00000000
53 00000000
54 00000000 ;=================
55 00000000 ; I/O PORT for LED
56 00000000 ;=================
57 00000000 56000050
GPFCON EQU 0x56000050 ;Port F control
58 00000000 56000054
GPFDAT EQU 0x56000054 ;Port F data
59 00000000 56000058
GPFUP EQU 0x56000058 ;Pull-up control F
60 00000000
61 00000000 56000010
GPBCON EQU 0x56000010 ;Port B control
62 00000000 56000014
GPBDAT EQU 0x56000014 ;Port B data
63 00000000
64 00000000
65 00000000 ;Miscellaneous register
66 00000000 56000080
MISCCR EQU 0x56000080 ;Miscellaneous cont
rol
67 00000000 56000084
DCKCON EQU 0x56000084 ;DCLK0/1 control
68 00000000 56000088
EXTINT0 EQU 0x56000088 ;External interrupt
control register 0
69 00000000 5600008C
EXTINT1 EQU 0x5600008c ;External interrupt
control register 1
70 00000000 56000090
EXTINT2 EQU 0x56000090 ;External interrupt
control register 2
71 00000000 56000094
EINTFLT0
EQU 0x56000094 ;Reserved
72 00000000 56000098
EINTFLT1
EQU 0x56000098 ;Reserved
73 00000000 5600009C
EINTFLT2
EQU 0x5600009c ;External interrupt
filter control reg
ister 2
74 00000000 560000A0
EINTFLT3
EQU 0x560000a0 ;External interrupt
filter control reg
ister 3
75 00000000 560000A4
EINTMASK
ARM Macro Assembler Page 4
EQU 0x560000a4 ;External interrupt
mask
76 00000000 560000A8
EINTPEND
EQU 0x560000a8 ;External interrupt
pending
77 00000000 560000AC
GSTATUS0
EQU 0x560000ac ;External pin statu
s
78 00000000 560000B0
GSTATUS1
EQU 0x560000b0 ;Chip ID(0x32440000
)
79 00000000 560000B4
GSTATUS2
EQU 0x560000b4 ;Reset type
80 00000000 560000B8
GSTATUS3
EQU 0x560000b8 ;Saved data0(32-bit
) before entering P
OWER_OFF mode
81 00000000 560000BC
GSTATUS4
EQU 0x560000bc ;Saved data1(32-bit
) before entering P
OWER_OFF mode
82 00000000
83 00000000 ;Added for 2440 ; DonGo
84 00000000 560000CC
MSLCON EQU 0x560000cc ;Memory sleep contr
ol register
85 00000000
86 00000000 ;=================
87 00000000 ; WATCH DOG TIMER
88 00000000 ;=================
89 00000000 53000000
WTCON EQU 0x53000000 ;Watch-dog timer mo
de
90 00000000 53000004
WTDAT EQU 0x53000004 ;Watch-dog timer da
ta
91 00000000 53000008
WTCNT EQU 0x53000008 ;Eatch-dog timer co
unt
92 00000000
93 00000000 ;=================
94 00000000 ; Nand Flash
95 00000000 ;=================
96 00000000 4E000000
NFCONF EQU 0x4E000000 ;NAND Flash configu
ration
97 00000000 4E000004
NFCONT EQU 0x4E000004 ;NAND Flash control
98 00000000 4E000008
NFCMD EQU 0x4E000008 ;NAND Flash command
99 00000000 4E00000C
ARM Macro Assembler Page 5
NFADDR EQU 0x4E00000C ;NAND Flash address
100 00000000 4E000010
NFDATA EQU 0x4E000010 ;NAND Flash data
101 00000000 4E000010
NFDATA8 EQU 0x4E000010 ;NAND Flash data
102 00000000 4E000014
NFMECCD0
EQU 0x4E000014 ;NAND Flash ECC for
Main Area
103 00000000 4E000018
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