📄 stack_init.lst
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ARM Macro Assembler Page 1
1 00000000 ;************************************
2 00000000 ;定义7中处理模式下的栈起始地址和大小
3 00000000 ;SDRAM地址范围：0x30000000~0x33FFFFFF
4 00000000 ;栈基址地址从0x33FFFFFF开始往后倒退
5 00000000 ;***********************************
6 00000000 AREA STACK, CODE, READONLY
7 00000000 ENTRY
8 00000000 CODE32
9 00000000 GET 2440addr.inc
1 00000000 ;=======================================================
=============
2 00000000 ; File Name : 2440addr.a
3 00000000 ; Function : S3C2440 Define Address Register (Assembly)
4 00000000 ; Date : March 27, 2002
5 00000000 ; Revision : Programming start (February 18,2002) -> SOP
6 00000000 ; Revision : 03.11.2003 ver 0.0 Attatched for 2440
7 00000000 ;=======================================================
=============
8 00000000
9 00000000 GBLL BIG_ENDIAN__
10 00000000 FALSE
BIG_ENDIAN__
SETL {FALSE}
11 00000000
12 00000000 ;=================
13 00000000 ; Memory control
14 00000000 ;=================
15 00000000 48000000
BWSCON EQU 0x48000000 ;Bus width & wait s
tatus
16 00000000 48000004
BANKCON0
EQU 0x48000004 ;Boot ROM control
17 00000000 48000008
BANKCON1
EQU 0x48000008 ;BANK1 control
18 00000000 4800000C
BANKCON2
EQU 0x4800000c ;BANK2 control
19 00000000 48000010
BANKCON3
EQU 0x48000010 ;BANK3 control
20 00000000 48000014
BANKCON4
EQU 0x48000014 ;BANK4 control
21 00000000 48000018
BANKCON5
EQU 0x48000018 ;BANK5 control
22 00000000 4800001C
BANKCON6
EQU 0x4800001c ;BANK6 control
23 00000000 48000020
BANKCON7
EQU 0x48000020 ;BANK7 control
24 00000000 48000024
REFRESH EQU 0x48000024 ;DRAM/SDRAM refresh
ARM Macro Assembler Page 2
25 00000000 48000028
BANKSIZE
EQU 0x48000028 ;Flexible Bank Size
26 00000000 4800002C
MRSRB6 EQU 0x4800002c ;Mode register set
for SDRAM Bank6
27 00000000 48000030
MRSRB7 EQU 0x48000030 ;Mode register set
for SDRAM Bank7
28 00000000
29 00000000
30 00000000 ;==========================
31 00000000 ; CLOCK & POWER MANAGEMENT
32 00000000 ;==========================
33 00000000 4C000000
LOCKTIME
EQU 0x4c000000 ;PLL lock time coun
ter
34 00000000 4C000004
MPLLCON EQU 0x4c000004 ;MPLL Control
35 00000000 4C000008
UPLLCON EQU 0x4c000008 ;UPLL Control
36 00000000 4C00000C
CLKCON EQU 0x4c00000c ;Clock generator co
ntrol
37 00000000 4C000010
CLKSLOW EQU 0x4c000010 ;Slow clock control
38 00000000 4C000014
CLKDIVN EQU 0x4c000014 ;Clock divider cont
rol
39 00000000
40 00000000
41 00000000 ;=================
42 00000000 ; INTERRUPT
43 00000000 ;=================
44 00000000 4A000000
SRCPND EQU 0x4a000000 ;Interrupt request
status
45 00000000 4A000004
INTMOD EQU 0x4a000004 ;Interrupt mode con
trol
46 00000000 4A000008
INTMSK EQU 0x4a000008 ;Interrupt mask con
trol
47 00000000 4A00000C
PRIORITY
EQU 0x4a00000c ;IRQ priority contr
ol <-- Ma
y 06, 2002 SOP
48 00000000 4A000010
INTPND EQU 0x4a000010 ;Interrupt request
status
49 00000000 4A000014
INTOFFSET
EQU 0x4a000014 ;Interruot request
source offset
50 00000000 4A000018
ARM Macro Assembler Page 3
SUBSRCPND
EQU 0x4a000018 ;Sub source pending
51 00000000 4A00001C
INTSUBMSK
EQU 0x4a00001c ;Interrupt sub mask
52 00000000
53 00000000
54 00000000 ;=================
55 00000000 ; I/O PORT for LED
56 00000000 ;=================
57 00000000 56000050
GPFCON EQU 0x56000050 ;Port F control
58 00000000 56000054
GPFDAT EQU 0x56000054 ;Port F data
59 00000000 56000058
GPFUP EQU 0x56000058 ;Pull-up control F
60 00000000
61 00000000 56000010
GPBCON EQU 0x56000010 ;Port B control
62 00000000 56000014
GPBDAT EQU 0x56000014 ;Port B data
63 00000000
64 00000000
65 00000000 ;Miscellaneous register
66 00000000 56000080
MISCCR EQU 0x56000080 ;Miscellaneous cont
rol
67 00000000 56000084
DCKCON EQU 0x56000084 ;DCLK0/1 control
68 00000000 56000088
EXTINT0 EQU 0x56000088 ;External interrupt
control register 0
69 00000000 5600008C
EXTINT1 EQU 0x5600008c ;External interrupt
control register 1
70 00000000 56000090
EXTINT2 EQU 0x56000090 ;External interrupt
control register 2
71 00000000 56000094
EINTFLT0
EQU 0x56000094 ;Reserved
72 00000000 56000098
EINTFLT1
EQU 0x56000098 ;Reserved
73 00000000 5600009C
EINTFLT2
EQU 0x5600009c ;External interrupt
filter control reg
ister 2
74 00000000 560000A0
EINTFLT3
EQU 0x560000a0 ;External interrupt
filter control reg
ister 3
ARM Macro Assembler Page 4
75 00000000 560000A4
EINTMASK
EQU 0x560000a4 ;External interrupt
mask
76 00000000 560000A8
EINTPEND
EQU 0x560000a8 ;External interrupt
pending
77 00000000 560000AC
GSTATUS0
EQU 0x560000ac ;External pin statu
s
78 00000000 560000B0
GSTATUS1
EQU 0x560000b0 ;Chip ID(0x32440000
)
79 00000000 560000B4
GSTATUS2
EQU 0x560000b4 ;Reset type
80 00000000 560000B8
GSTATUS3
EQU 0x560000b8 ;Saved data0(32-bit
) before entering P
OWER_OFF mode
81 00000000 560000BC
GSTATUS4
EQU 0x560000bc ;Saved data1(32-bit
) before entering P
OWER_OFF mode
82 00000000
83 00000000 ;Added for 2440 ; DonGo
84 00000000 560000CC
MSLCON EQU 0x560000cc ;Memory sleep contr
ol register
85 00000000
86 00000000 ;=================
87 00000000 ; WATCH DOG TIMER
88 00000000 ;=================
89 00000000 53000000
WTCON EQU 0x53000000 ;Watch-dog timer mo
de
90 00000000 53000004
WTDAT EQU 0x53000004 ;Watch-dog timer da
ta
91 00000000 53000008
WTCNT EQU 0x53000008 ;Eatch-dog timer co
unt
92 00000000
93 00000000 ;=================
94 00000000 ; Nand Flash
95 00000000 ;=================
96 00000000 4E000000
NFCONF EQU 0x4E000000 ;NAND Flash configu
ration
97 00000000 4E000004
NFCONT EQU 0x4E000004 ;NAND Flash control
98 00000000 4E000008
NFCMD EQU 0x4E000008 ;NAND Flash command
ARM Macro Assembler Page 5
99 00000000 4E00000C
NFADDR EQU 0x4E00000C ;NAND Flash address
100 00000000 4E000010
NFDATA EQU 0x4E000010 ;NAND Flash data
101 00000000 4E000010
NFDATA8 EQU 0x4E000010 ;NAND Flash data
102 00000000 4E000014
NFMECCD0
EQU 0x4E000014 ;NAND Flash ECC for
Main Area
103 00000000 4E000018
NFMECCD1
EQU 0x4E000018
104 00000000 4E00001C
NFSECCD EQU 0x4E00001C ;NAND Flash ECC for
Spare Area
105 00000000 4E000020
NFSTAT EQU 0x4E000020 ;NAND Flash operati
on status
106 00000000 4E000024
NFESTAT0
EQU 0x4E000024
107 00000000 4E000028
NFESTAT1
EQU 0x4E000028
108 00000000 4E00002C
NFMECC0 EQU 0x4E00002C
109 00000000 4E000030
NFMECC1 EQU 0x4E000030
110 00000000 4E000034
NFSECC EQU 0x4E000034
111 00000000 4E000038
NFSBLK EQU 0x4E000038 ;NAND Flash Start b
lock address
112 00000000 4E00003C
NFEBLK EQU 0x4E00003C ;NAND Flash End blo
ck address
113 00000000
114 00000000 END
10 00000000 EXPORT InitStack
11 00000000
12 00000000
13 00000000 33FF0000
C_STACK_BASE
EQU 0X33FF0000
14 00000000 33FF0000
C_USR_STACK_BASE
EQU C_STACK_BASE
15 00000000 00002800
C_USR_STACK_SIZE
EQU (10*1024)
16 00000000 33FED800
C_SYS_STACK_BASE
EQU C_USR_STACK_BASE - C_USR_STACK_
SIZE
17 00000000 00002800
C_SYS_STACK_SIZE
ARM Macro Assembler Page 6
EQU (10*1024)
18 00000000 33FEB000
C_SVC_STACK_BASE
EQU C_SYS_STACK_BASE - C_SYS_STACK_
SIZE
19 00000000 00002800
C_SVC_STACK_SIZE
EQU (10*1024)
20 00000000 33FE8800
C_IRQ_STACK_BASE
EQU C_SVC_STACK_BASE - C_SVC_STACK_
SIZE
21 00000000 00002800
C_IRQ_STACK_SIZE
EQU (10*1024)
22 00000000 33FE6000
C_FIQ_STACK_BASE
EQU C_IRQ_STACK_BASE - C_IRQ_STACK_
SIZE
23 00000000 00000400
C_FIQ_STACK_SIZE
EQU (1024)
24 00000000 33FE5C00
C_ABT_STACK_BASE
EQU C_FIQ_STACK_BASE - C_FIQ_STACK_
SIZE
25 00000000 00000080
C_ABT_STACK_SIZE
EQU (128)
26 00000000 33FE5B80
C_UND_STACK_BASE
EQU C_ABT_STACK_BASE - C_ABT_STACK_
SIZE
27 00000000 00000080
C_UND_STACK_SIZE
EQU (128)
28 00000000
29 00000000
30 00000000 ;*******************************************************
*********
31 00000000 ;配置各种模式下的堆栈
32 00000000 ;*******************************************************
*********
33 00000000
34 00000000 InitStack
35 00000000 E10F7000 MRS R7, CPSR ;备份处理器模式
36 00000004
37 00000004 E10F0000 MRS R0, CPSR
38 00000008 E3C0001F AND R0, R0, #0XFFFFFFE0
39 0000000C
40 0000000C ;配置SVC模式的堆栈
41 0000000C E3801013 ORR R1, R0, #0X13
42 00000010 E121F001 MSR CPSR_c, R1
43 00000014 E59FD040 LDR SP, =C_SVC_STACK_BASE
44 00000018
45 00000018 ;配置IRQ模式的堆栈
46 00000018 E3801012 ORR R1, R0, #0X12
47 0000001C E121F001 MSR CPSR_c, R1
48 00000020 E59FD038 LDR SP, =C_IRQ_STACK_BASE
ARM Macro Assembler Page 7
49 00000024
50 00000024 ;配置FIQ模式的堆栈
51 00000024 E3801011 ORR R1, R0, #0X11
52 00000028 E121F001 MSR CPSR_c, R1
53 0000002C E59FD030 LDR SP, =C_FIQ_STACK_BASE
54 00000030
55 00000030 ;配置UND模式的堆栈
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