pll_init.lst

ucos_ii在mini2440上的移植KEIL编译环境

                                                             filter control reg
                                                            ister 3
   75 00000000 560000A4 



ARM Macro Assembler    Page 4 


                       EINTMASK
                               EQU              0x560000a4  ;External interrupt
                                                             mask
   76 00000000 560000A8 
                       EINTPEND
                               EQU              0x560000a8  ;External interrupt
                                                             pending
   77 00000000 560000AC 
                       GSTATUS0
                               EQU              0x560000ac  ;External pin statu
                                                            s
   78 00000000 560000B0 
                       GSTATUS1
                               EQU              0x560000b0  ;Chip ID(0x32440000
                                                            )
   79 00000000 560000B4 
                       GSTATUS2
                               EQU              0x560000b4  ;Reset type
   80 00000000 560000B8 
                       GSTATUS3
                               EQU              0x560000b8  ;Saved data0(32-bit
                                                            ) before entering P
                                                            OWER_OFF mode
   81 00000000 560000BC 
                       GSTATUS4
                               EQU              0x560000bc  ;Saved data1(32-bit
                                                            ) before entering P
                                                            OWER_OFF mode
   82 00000000         
   83 00000000         ;Added for 2440     ; DonGo
   84 00000000 560000CC 
                       MSLCON  EQU              0x560000cc  ;Memory sleep contr
                                                            ol register
   85 00000000         
   86 00000000         ;=================
   87 00000000         ; WATCH DOG TIMER
   88 00000000         ;=================
   89 00000000 53000000 
                       WTCON   EQU              0x53000000  ;Watch-dog timer mo
                                                            de
   90 00000000 53000004 
                       WTDAT   EQU              0x53000004  ;Watch-dog timer da
                                                            ta
   91 00000000 53000008 
                       WTCNT   EQU              0x53000008  ;Eatch-dog timer co
                                                            unt
   92 00000000         
   93 00000000         ;=================
   94 00000000         ; Nand Flash
   95 00000000         ;=================
   96 00000000 4E000000 
                       NFCONF  EQU              0x4E000000  ;NAND Flash configu
                                                            ration
   97 00000000 4E000004 
                       NFCONT  EQU              0x4E000004  ;NAND Flash control
                                                            
   98 00000000 4E000008 
                       NFCMD   EQU              0x4E000008  ;NAND Flash command
                                                            



ARM Macro Assembler    Page 5 


   99 00000000 4E00000C 
                       NFADDR  EQU              0x4E00000C  ;NAND Flash address
                                                            
  100 00000000 4E000010 
                       NFDATA  EQU              0x4E000010  ;NAND Flash data
  101 00000000 4E000010 
                       NFDATA8 EQU              0x4E000010  ;NAND Flash data
  102 00000000 4E000014 
                       NFMECCD0
                               EQU              0x4E000014  ;NAND Flash ECC for
                                                             Main Area
  103 00000000 4E000018 
                       NFMECCD1
                               EQU              0x4E000018
  104 00000000 4E00001C 
                       NFSECCD EQU              0x4E00001C  ;NAND Flash ECC for
                                                             Spare Area
  105 00000000 4E000020 
                       NFSTAT  EQU              0x4E000020  ;NAND Flash operati
                                                            on status
  106 00000000 4E000024 
                       NFESTAT0
                               EQU              0x4E000024
  107 00000000 4E000028 
                       NFESTAT1
                               EQU              0x4E000028
  108 00000000 4E00002C 
                       NFMECC0 EQU              0x4E00002C
  109 00000000 4E000030 
                       NFMECC1 EQU              0x4E000030
  110 00000000 4E000034 
                       NFSECC  EQU              0x4E000034
  111 00000000 4E000038 
                       NFSBLK  EQU              0x4E000038  ;NAND Flash Start b
                                                            lock address
  112 00000000 4E00003C 
                       NFEBLK  EQU              0x4E00003C  ;NAND Flash End blo
                                                            ck address
  113 00000000         
  114 00000000                 END
    9 00000000                 EXPORT           InitPLL
   10 00000000         
   11 00000000         ;UPLL时钟配置，UPLL只能48MHz或48MHz
   12 00000000 00000038 
                       UPLL_MDIV_VAL
                               EQU              0X38
   13 00000000 00000002 
                       UPLL_PDIV_VAL
                               EQU              0X2
   14 00000000 00000002 
                       UPLL_SDIV_VAL
                               EQU              0X2
   15 00000000 00038000 
                       UPLL_MDIV
                               EQU              (UPLL_MDIV_VAL << 12)
   16 00000000 00000020 
                       UPLL_PDIV
                               EQU              (UPLL_PDIV_VAL << 4)
   17 00000000 00000002 



ARM Macro Assembler    Page 6 


                       UPLL_SDIV
                               EQU              (UPLL_SDIV_VAL << 0)
   18 00000000 00000000 
                       DIVN_UPLL
                               EQU              0
   19 00000000         
   20 00000000         ;MPLL时钟配置，MPLL在200MHz-600MHz
   21 00000000 00000044 
                       MPLL_MDIV_VAL
                               EQU              0X44
   22 00000000 00000001 
                       MPLL_PDIV_VAL
                               EQU              1
   23 00000000 00000001 
                       MPLL_SDIV_VAL
                               EQU              1
   24 00000000 00044000 
                       MPLL_MDIV
                               EQU              (MPLL_MDIV_VAL << 12)
   25 00000000 00000010 
                       MPLL_PDIV
                               EQU              (MPLL_PDIV_VAL << 4)
   26 00000000 00000001 
                       MPLL_SDIV
                               EQU              (MPLL_SDIV_VAL << 0)
   27 00000000         
   28 00000000 00000003 
                       HDIVN   EQU              3
   29 00000000 00000001 
                       PDIVN   EQU              1
   30 00000000         
   31 00000000 00038022 
                       UPLL_VAL
                               EQU              (UPLL_MDIV | UPLL_PDIV | UPLL_S
DIV)
   32 00000000 00044011 
                       MPLL_VAL
                               EQU              (MPLL_MDIV | MPLL_PDIV | MPLL_S
DIV)
   33 00000000 00000007 
                       CLKDIVN_VAL
                               EQU              ((DIVN_UPLL << 3) | (HDIVN << 1
) | (PDIVN << 0))
   34 00000000         
   35 00000000         ;以上配置产生的MPLL时钟频率如下
   36 00000000         ;FCLK   EQU 304
   37 00000000         ;HCLK   EQU 101
   38 00000000         ;PCLK   EQU 50
   39 00000000         
   40 00000000         ;系统时钟MPLL和UPLL配置 
   41 00000000         InitPLL
   42 00000000 E3A00313        LDR              R0, =LOCKTIME ;配置PLL的稳定周