📄 multint2.c
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/*********************************************************************
* Filename: MULTINT2.c *
* *
* Description: Checks the ability of the CAN module to service
* multiple interrupts automatically.
All 32 mailboxes are allowed to transmit and then the interrupts enabled
A counter in the ISR counts the # of times an interrupt was asserted.
The same interupt line (eCANINT0 or eCANINT1) is used.
* Last update: 12/26/2002
*********************************************************************/
#include "DSP281x_Device.h"
// Prototype statements for functions found within this file.
interrupt void eCAN0INT_ISR(void);
interrupt void eCAN1INT_ISR(void);
// Variable declarations
int int0count = 0; // Counter to track the # of level 0 interrupts
int int1count = 0; // Counter to track the # of level 1 interrupts
int16 buffer = 0;
long i;
void InitECan(void);
int MIV = 0; // Stores the mailbox # that needs to be serviced.
/* Create a shadow register structure for the CAN control registers. This is
needed, since, only 32-bit access is allowed to these registers. 16-bit access
to these registers could potentially corrupt the register contents. This is
especially true while writing to a bit (or group of bits) among bits 16 - 31 */
struct ECAN_REGS ECanaShadow;
main()
{
/* Initialize the CAN module */
InitECan();
/* Initialize PIE vector table To a Known State: */
// The PIE vector table is initialized with pointers to shell "Interrupt
// Service Routines (ISR)". The shell routines are found in DSP28_DefaultIsr.c.
// Insert user specific ISR code in the appropriate shell ISR routine in
// the DSP28_DefaultIsr.c file.
// InitPieVectTable(); // uncomment this line if the shell ISR routines are needed
// This function is found in DSP28_PieVect.c. It populates the PIE vector table
// with pointers to the shell ISR functions found in DSP28_DefaultIsr.c. This
// function is not useful in this code because the user-specific ISR is present
// in this file itself. The shell ISR routine in the DSP28_DefaultIsr.c file is
// not used. If the shell ISR routines are needed, uncomment this line and add
// DSP28_PieVect.c & DSP28_DefaultIsr.c files to the project
/* Disable and clear all CPU interrupts: */
DINT; // Note that InitPieCtrl() enables interrupts
IER = 0x0000;
IFR = 0x0000;
/* Initialize Pie Control Registers To Default State */
InitPieCtrl(); // This function is found in the DSP28_PieCtrl.c file.
DINT; // Disable interrupts again (for now)
/* Write to the MSGID field of TRANSMIT mailboxes MBOX0 - 31 */
ECanaMboxes.MBOX0.MSGID.all = 0x9555AAA0;
ECanaMboxes.MBOX1.MSGID.all = 0x9555AAA1;
ECanaMboxes.MBOX2.MSGID.all = 0x9555AAA2;
ECanaMboxes.MBOX3.MSGID.all = 0x9555AAA3;
ECanaMboxes.MBOX4.MSGID.all = 0x9555AAA4;
ECanaMboxes.MBOX5.MSGID.all = 0x9555AAA5;
ECanaMboxes.MBOX6.MSGID.all = 0x9555AAA6;
ECanaMboxes.MBOX7.MSGID.all = 0x9555AAA7;
ECanaMboxes.MBOX8.MSGID.all = 0x9555AAA8;
ECanaMboxes.MBOX9.MSGID.all = 0x9555AAA9;
ECanaMboxes.MBOX10.MSGID.all = 0x9555AA10;
ECanaMboxes.MBOX11.MSGID.all = 0x9555AA11;
ECanaMboxes.MBOX12.MSGID.all = 0x9555AA12;
ECanaMboxes.MBOX13.MSGID.all = 0x9555AA13;
ECanaMboxes.MBOX14.MSGID.all = 0x9555AA14;
ECanaMboxes.MBOX15.MSGID.all = 0x9555AA15;
ECanaMboxes.MBOX16.MSGID.all = 0x9555AA16;
ECanaMboxes.MBOX17.MSGID.all = 0x9555AA17;
ECanaMboxes.MBOX18.MSGID.all = 0x9555AA18;
ECanaMboxes.MBOX19.MSGID.all = 0x9555AA19;
ECanaMboxes.MBOX20.MSGID.all = 0x9555AA20;
ECanaMboxes.MBOX21.MSGID.all = 0x9555AA21;
ECanaMboxes.MBOX22.MSGID.all = 0x9555AA22;
ECanaMboxes.MBOX23.MSGID.all = 0x9555AA23;
ECanaMboxes.MBOX24.MSGID.all = 0x9555AA24;
ECanaMboxes.MBOX25.MSGID.all = 0x9555AA25;
ECanaMboxes.MBOX26.MSGID.all = 0x9555AA26;
ECanaMboxes.MBOX27.MSGID.all = 0x9555AA27;
ECanaMboxes.MBOX28.MSGID.all = 0x9555AA28;
ECanaMboxes.MBOX29.MSGID.all = 0x9555AA29;
ECanaMboxes.MBOX30.MSGID.all = 0x9555AA30;
ECanaMboxes.MBOX31.MSGID.all = 0x9555AA31;
/* Configure Mailboxes 0-31 as Tx */
ECanaRegs.CANMD.all = 0xffffffff;
/* Enable all Mailboxes */
ECanaRegs.CANME.all = 0xFFFFFFFF;
/* Write to Master Control field - DLC */
ECanaMboxes.MBOX0.MCF.bit.DLC = 8;
ECanaMboxes.MBOX1.MCF.bit.DLC = 8;
ECanaMboxes.MBOX2.MCF.bit.DLC = 8;
ECanaMboxes.MBOX3.MCF.bit.DLC = 8;
ECanaMboxes.MBOX4.MCF.bit.DLC = 8;
ECanaMboxes.MBOX5.MCF.bit.DLC = 8;
ECanaMboxes.MBOX6.MCF.bit.DLC = 8;
ECanaMboxes.MBOX7.MCF.bit.DLC = 8;
ECanaMboxes.MBOX8.MCF.bit.DLC = 8;
ECanaMboxes.MBOX9.MCF.bit.DLC = 8;
ECanaMboxes.MBOX10.MCF.bit.DLC = 8;
ECanaMboxes.MBOX11.MCF.bit.DLC = 8;
ECanaMboxes.MBOX12.MCF.bit.DLC = 8;
ECanaMboxes.MBOX13.MCF.bit.DLC = 8;
ECanaMboxes.MBOX14.MCF.bit.DLC = 8;
ECanaMboxes.MBOX15.MCF.bit.DLC = 8;
ECanaMboxes.MBOX16.MCF.bit.DLC = 8;
ECanaMboxes.MBOX17.MCF.bit.DLC = 8;
ECanaMboxes.MBOX18.MCF.bit.DLC = 8;
ECanaMboxes.MBOX19.MCF.bit.DLC = 8;
ECanaMboxes.MBOX20.MCF.bit.DLC = 8;
ECanaMboxes.MBOX21.MCF.bit.DLC = 8;
ECanaMboxes.MBOX22.MCF.bit.DLC = 8;
ECanaMboxes.MBOX23.MCF.bit.DLC = 8;
ECanaMboxes.MBOX24.MCF.bit.DLC = 8;
ECanaMboxes.MBOX25.MCF.bit.DLC = 8;
ECanaMboxes.MBOX26.MCF.bit.DLC = 8;
ECanaMboxes.MBOX27.MCF.bit.DLC = 8;
ECanaMboxes.MBOX28.MCF.bit.DLC = 8;
ECanaMboxes.MBOX29.MCF.bit.DLC = 8;
ECanaMboxes.MBOX30.MCF.bit.DLC = 8;
ECanaMboxes.MBOX31.MCF.bit.DLC = 8;
/* Write to the mailbox RAM field of MBOX0 - 31 */
ECanaMboxes.MBOX0.MDRL.all = 0x9555AAA0;
ECanaMboxes.MBOX0.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX1.MDRL.all = 0x9555AAA1;
ECanaMboxes.MBOX1.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX2.MDRL.all = 0x9555AAA2;
ECanaMboxes.MBOX2.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX3.MDRL.all = 0x9555AAA3;
ECanaMboxes.MBOX3.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX4.MDRL.all = 0x9555AAA4;
ECanaMboxes.MBOX4.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX5.MDRL.all = 0x9555AAA5;
ECanaMboxes.MBOX5.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX6.MDRL.all = 0x9555AAA6;
ECanaMboxes.MBOX6.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX7.MDRL.all = 0x9555AAA7;
ECanaMboxes.MBOX7.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX8.MDRL.all = 0x9555AAA8;
ECanaMboxes.MBOX8.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX9.MDRL.all = 0x9555AAA9;
ECanaMboxes.MBOX9.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX10.MDRL.all = 0x9555AAAA;
ECanaMboxes.MBOX10.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX11.MDRL.all = 0x9555AAAB;
ECanaMboxes.MBOX11.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX12.MDRL.all = 0x9555AAAC;
ECanaMboxes.MBOX12.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX13.MDRL.all = 0x9555AAAD;
ECanaMboxes.MBOX13.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX14.MDRL.all = 0x9555AAAE;
ECanaMboxes.MBOX14.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX15.MDRL.all = 0x9555AAAF;
ECanaMboxes.MBOX15.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX16.MDRL.all = 0x9555AA10;
ECanaMboxes.MBOX16.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX17.MDRL.all = 0x9555AA11;
ECanaMboxes.MBOX17.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX18.MDRL.all = 0x9555AA12;
ECanaMboxes.MBOX18.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX19.MDRL.all = 0x9555AA13;
ECanaMboxes.MBOX19.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX20.MDRL.all = 0x9555AA14;
ECanaMboxes.MBOX20.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX21.MDRL.all = 0x9555AA15;
ECanaMboxes.MBOX21.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX22.MDRL.all = 0x9555AA16;
ECanaMboxes.MBOX22.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX23.MDRL.all = 0x9555AA17;
ECanaMboxes.MBOX23.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX24.MDRL.all = 0x9555AA18;
ECanaMboxes.MBOX24.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX25.MDRL.all = 0x9555AA19;
ECanaMboxes.MBOX25.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX26.MDRL.all = 0x9555AA1A;
ECanaMboxes.MBOX26.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX27.MDRL.all = 0x9555AA1B;
ECanaMboxes.MBOX27.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX28.MDRL.all = 0x9555AA1C;
ECanaMboxes.MBOX28.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX29.MDRL.all = 0x9555AA1D;
ECanaMboxes.MBOX29.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX30.MDRL.all = 0x9555AA1E;
ECanaMboxes.MBOX30.MDRH.all = 0x89ABCDEF;
ECanaMboxes.MBOX31.MDRL.all = 0x9555AA1F;
ECanaMboxes.MBOX31.MDRH.all = 0x89ABCDEF;
ECanaRegs.CANMIM.all = 0xFFFFFFFF;
/* Configure CAN interrupts */
ECanaShadow.CANMIL.all = 0xFFFFFFFF ; // Interrupts asserted on eCAN1INT
//ECanaShadow.CANMIL.all = 0x00000000 ; // Interrupts asserted on eCAN0INT
ECanaRegs.CANMIL.all = ECanaShadow.CANMIL.all;
ECanaShadow.CANMIM.all = 0xFFFFFFFF; // Enable interrupts for all mailboxes
ECanaRegs.CANMIM.all = ECanaShadow.CANMIM.all;
ECanaShadow.CANGIM.all = 0;
// ECanaShadow.CANGIM.bit.I0EN = 1; // Enable eCAN1INT or eCAN0INT
ECanaShadow.CANGIM.bit.I1EN = 1;
ECanaRegs.CANGIM.all = ECanaShadow.CANGIM.all;
/* Reassign ISRs. i.e. reassign the PIE vector for ECAN0INTA_ISR and ECAN0INTA_ISR
to point to a different ISR than the shell routine found in DSP28_DefaultIsr.c.
This is done if the user does not want to use the shell ISR routine but instead
wants to embed the ISR in this file itself. */
PieVectTable.ECAN0INTA = &eCAN0INT_ISR;
PieVectTable.ECAN1INTA = &eCAN1INT_ISR;
/* Configure PIE interrupts */
PieCtrlRegs.PIECRTL.bit.ENPIE = 1; // Enable vector fetching from PIE block
PieCtrlRegs.PIEACK.bit.ACK9 = 1; // Enables PIE to drive a pulse into the CPU
// The interrupt can be asserted in either of the eCAN interrupt lines
// Comment out the unwanted line...
PieCtrlRegs.PIEIER9.bit.INTx5 = 0; // Enable INTx.5 of INT9 (eCAN0INT)
PieCtrlRegs.PIEIER9.bit.INTx6 = 1; // Enable INTx.6 of INT9 (eCAN1INT)
/* Configure system interrupts */
IER |= 0x0100; // Enable INT9 of CPU
/* Begin transmitting */
// ECanaRegs.CANTA.all = 0xFFFFFFFF; // Clear all "set" TAn bits, if any
// ECanaRegs.CANTRS.all = 0xFFFFFFFF; // Set TRS for all mailboxes
// while(ECanaRegs.CANRMP.all != 0xFFFFFFFF) {}
EINT; // Global enable of interrupts
while(1) {}
}
/* --------------------------------------------------- */
/* ISR for PIE INT9.5 (MBX30) */
/* Connected to eCAN0-INTA eCAN */
/* ----------------------------------------------------*/
interrupt void eCAN0INT_ISR(void) // eCAN
{
ECanaShadow.CANRMP.all = 0 ;
//ECanaRegs.CANTA.all = ECanaShadow.CANTA.all ;
int0count++;
PieCtrlRegs.PIEACK.bit.ACK9 = 1; // Enables PIE to drive a pulse into the CPU
IER |= 0x0100; // Enable INT9
EINT;
return;
}
/* --------------------------------------------------- */
/* ISR for PIE INT9.6 (MBX5) */
/* Connected to eCAN1-INTA eCAN */
/* ----------------------------------------------------*/
interrupt void eCAN1INT_ISR(void) // eCAN
{
asm (" NOP");
ECanaShadow.CANRMP.all = 0;
ECanaShadow.CANRMP.all = 0xFFFFFFFF;
ECanaRegs.CANRMP.all = ECanaShadow.CANRMP.all ;
// ECanaShadow.CANTA.all = ECanaRegs.CANTA.all ;
buffer = ECanaMboxes.MBOX0.MDRL.bit.LOW_WORD;
int1count++;
PieCtrlRegs.PIEACK.bit.ACK9 = 1; // Enables PIE to drive a pulse into the CPU
IER |= 0x0100; // Enable INT9
EINT;
return;
}
/*
* This example shows how when an interrupt flag is set while another
* interrupt flag is already set, the most recent interrupt flag automatically
* generates a core level interrupt upon exiting the ISR of the previous interrupt.
Case 2: All 32 mailboxes are allowed to transmit. It is then checked
whether interrupts were asserted 32 times.
(Only 6 mailboxes are checked and hence interrupt is asserted 6 times )
* It can be verified that every time a mailbox interrupt is asserted,
* bits[0..4] of the "Global Interrupt Flag" Register contains the
* mailbox number causing the interrupt. If more interrupt flags are
* pending, it contains the mailbox number with the highest priority.
* This is done as follows: Disable interrupts and let many mailboxes
* transmit messages. Now enable interrupts. A core level interrupt is
* asserted and upon entering the ISR, examine MIVn bits. It
* reflects the mailbox number with higher priority.
*/
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