io_map.c

FreeRTOSV4.1.0 安裝文件 FreeRTOS 是一个源码公开的免费的嵌入式实时操作系统

volatile PPSMSTR _PPSM;                                    /* Port M Polarity Select Register */
volatile PPSPSTR _PPSP;                                    /* Port P Polarity Select Register */
volatile PPSSSTR _PPSS;                                    /* Port S Polarity Select Register */
volatile PPSTSTR _PPST;                                    /* Port T Polarity Select Register */
volatile PTHSTR _PTH;                                      /* Port H I/O Register */
volatile PTIHSTR _PTIH;                                    /* Port H Input Register */
volatile PTIJSTR _PTIJ;                                    /* Port J Input Register */
volatile PTIMSTR _PTIM;                                    /* Port M Input */
volatile PTIPSTR _PTIP;                                    /* Port P Input */
volatile PTISSTR _PTIS;                                    /* Port S Input */
volatile PTITSTR _PTIT;                                    /* Port T Input */
volatile PTJSTR _PTJ;                                      /* Port J I/O Register */
volatile PTMSTR _PTM;                                      /* Port M I/O Register */
volatile PTPSTR _PTP;                                      /* Port P I/O Register */
volatile PTSSTR _PTS;                                      /* Port S I/O Register */
volatile PTTSTR _PTT;                                      /* Port T I/O Register */
volatile PUCRSTR _PUCR;                                    /* Pull-Up Control Register */
volatile PWMCAESTR _PWMCAE;                                /* PWM Center Align Enable Register */
volatile PWMCLKSTR _PWMCLK;                                /* PWM Clock Select Register */
volatile PWMCTLSTR _PWMCTL;                                /* PWM Control Register */
volatile PWMESTR _PWME;                                    /* PWM Enable Register */
volatile PWMPOLSTR _PWMPOL;                                /* PWM Polarity Register */
volatile PWMPRCLKSTR _PWMPRCLK;                            /* PWM Prescale Clock Select Register */
volatile PWMSCLASTR _PWMSCLA;                              /* PWM Scale A Register */
volatile PWMSCLBSTR _PWMSCLB;                              /* PWM Scale B Register */
volatile PWMSDNSTR _PWMSDN;                                /* PWM Shutdown Register */
volatile RDRHSTR _RDRH;                                    /* Port H Reduced Drive Register */
volatile RDRIVSTR _RDRIV;                                  /* Reduced Drive of I/O Lines */
volatile RDRJSTR _RDRJ;                                    /* Port J Reduced Drive Register */
volatile RDRMSTR _RDRM;                                    /* Port M Reduced Drive Register */
volatile RDRPSTR _RDRP;                                    /* Port P Reduced Drive Register */
volatile RDRSSTR _RDRS;                                    /* Port S Reduced Drive Register */
volatile RDRTSTR _RDRT;                                    /* Port T Reduced Drive Register */
volatile REFDVSTR _REFDV;                                  /* CRG Reference Divider Register */
volatile RTICTLSTR _RTICTL;                                /* CRG RTI Control Register */
volatile SCI0CR1STR _SCI0CR1;                              /* SCI 0 Control Register 1 */
volatile SCI0CR2STR _SCI0CR2;                              /* SCI 0 Control Register 2 */
volatile SCI0DRHSTR _SCI0DRH;                              /* SCI 0 Data Register High */
volatile SCI0DRLSTR _SCI0DRL;                              /* SCI 0 Data Register Low */
volatile SCI0SR1STR _SCI0SR1;                              /* SCI 0 Status Register 1 */
volatile SCI0SR2STR _SCI0SR2;                              /* SCI 0 Status Register 2 */
volatile SCI1CR1STR _SCI1CR1;                              /* SCI 1 Control Register 1 */
volatile SCI1CR2STR _SCI1CR2;                              /* SCI 1 Control Register 2 */
volatile SCI1DRHSTR _SCI1DRH;                              /* SCI 1 Data Register High */
volatile SCI1DRLSTR _SCI1DRL;                              /* SCI 1 Data Register Low */
volatile SCI1SR1STR _SCI1SR1;                              /* SCI 1 Status Register 1 */
volatile SCI1SR2STR _SCI1SR2;                              /* SCI 1 Status Register 2 */
volatile SPI0BRSTR _SPI0BR;                                /* SPI 0 Baud Rate Register */
volatile SPI0CR1STR _SPI0CR1;                              /* SPI 0 Control Register */
volatile SPI0CR2STR _SPI0CR2;                              /* SPI 0 Control Register 2 */
volatile SPI0DRSTR _SPI0DR;                                /* SPI 0 Data Register */
volatile SPI0SRSTR _SPI0SR;                                /* SPI 0 Status Register */
volatile SPI1BRSTR _SPI1BR;                                /* SPI 1 Baud Rate Register */
volatile SPI1CR1STR _SPI1CR1;                              /* SPI 1 Control Register */
volatile SPI1CR2STR _SPI1CR2;                              /* SPI 1 Control Register 2 */
volatile SPI1DRSTR _SPI1DR;                                /* SPI 1 Data Register */
volatile SPI1SRSTR _SPI1SR;                                /* SPI 1 Status Register */
volatile SPI2BRSTR _SPI2BR;                                /* SPI 2 Baud Rate Register */
volatile SPI2CR1STR _SPI2CR1;                              /* SPI 2 Control Register */
volatile SPI2CR2STR _SPI2CR2;                              /* SPI 2 Control Register 2 */
volatile SPI2DRSTR _SPI2DR;                                /* SPI 2 Data Register */
volatile SPI2SRSTR _SPI2SR;                                /* SPI 2 Status Register */
volatile SYNRSTR _SYNR;                                    /* CRG Synthesizer Register */
volatile TCTL1STR _TCTL1;                                  /* Timer Control Registers 1 */
volatile TCTL2STR _TCTL2;                                  /* Timer Control Registers 2 */
volatile TCTL3STR _TCTL3;                                  /* Timer Control Register 3 */
volatile TCTL4STR _TCTL4;                                  /* Timer Control Register 4 */
volatile TFLG1STR _TFLG1;                                  /* Main Timer Interrupt Flag 1 */
volatile TFLG2STR _TFLG2;                                  /* Main Timer Interrupt Flag 2 */
volatile TIESTR _TIE;                                      /* Timer Interrupt Enable Register */
volatile TIMTSTSTR _TIMTST;                                /* Timer Test Register */
volatile TIOSSTR _TIOS;                                    /* Timer Input Capture/Output Compare Select */
volatile TSCR1STR _TSCR1;                                  /* Timer System Control Register1 */
volatile TSCR2STR _TSCR2;                                  /* Timer System Control Register 2 */
volatile TTOVSTR _TTOV;                                    /* Timer Toggle On Overflow Register */
volatile WOMMSTR _WOMM;                                    /* Port M Wired-Or Mode Register */
volatile WOMSSTR _WOMS;                                    /* Port S Wired-Or Mode Register */
volatile ATD0CTL23STR _ATD0CTL23;                          /* ATD 0 Control Register 23 */
volatile ATD0CTL45STR _ATD0CTL45;                          /* ATD 0 Control Register 45 */
volatile ATD0DR0STR _ATD0DR0;                              /* ATD 0 Conversion Result Register 0 */
volatile ATD0DR1STR _ATD0DR1;                              /* ATD 0 Conversion Result Register 1 */
volatile ATD0DR2STR _ATD0DR2;                              /* ATD 0 Conversion Result Register 2 */
volatile ATD0DR3STR _ATD0DR3;                              /* ATD 0 Conversion Result Register 3 */
volatile ATD0DR4STR _ATD0DR4;                              /* ATD 0 Conversion Result Register 4 */
volatile ATD0DR5STR _ATD0DR5;                              /* ATD 0 Conversion Result Register 5 */
volatile ATD0DR6STR _ATD0DR6;                              /* ATD 0 Conversion Result Register 6 */
volatile ATD0DR7STR _ATD0DR7;                              /* ATD 0 Conversion Result Register 7 */
volatile ATD1CTL23STR _ATD1CTL23;                          /* ATD 1 Control Register 23 */
volatile ATD1CTL45STR _ATD1CTL45;                          /* ATD 1 Control Register 45 */
volatile ATD1DR0STR _ATD1DR0;                              /* ATD 1 Conversion Result Register 0 */
volatile ATD1DR1STR _ATD1DR1;                              /* ATD 1 Conversion Result Register 1 */
volatile ATD1DR2STR _ATD1DR2;                              /* ATD 1 Conversion Result Register 2 */
volatile ATD1DR3STR _ATD1DR3;                              /* ATD 1 Conversion Result Register 3 */
volatile ATD1DR4STR _ATD1DR4;                              /* ATD 1 Conversion Result Register 4 */
volatile ATD1DR5STR _ATD1DR5;                              /* ATD 1 Conversion Result Register 5 */
volatile ATD1DR6STR _ATD1DR6;                              /* ATD 1 Conversion Result Register 6 */
volatile ATD1DR7STR _ATD1DR7;                              /* ATD 1 Conversion Result Register 7 */
volatile DDRABSTR _DDRAB;                                  /* Port AB Data Direction Register */
volatile MCCNTSTR _MCCNT;                                  /* Modulus Down-Counter Count Register */
volatile PA10HSTR _PA10H;                                  /* 8-Bit Pulse Accumulators Holding 10 Register */
volatile PA32HSTR _PA32H;                                  /* 8-Bit Pulse Accumulators Holding 32 Register */
volatile PACN10STR _PACN10;                                /* Pulse Accumulators Count 10 Register */
volatile PACN32STR _PACN32;                                /* Pulse Accumulators Count 32 Register */
volatile PORTABSTR _PORTAB;                                /* Port AB Register */
volatile PWMCNT01STR _PWMCNT01;                            /* PWM Channel Counter 01 Register */
volatile PWMCNT23STR _PWMCNT23;                            /* PWM Channel Counter 23 Register */
volatile PWMCNT45STR _PWMCNT45;                            /* PWM Channel Counter 45 Register */
volatile PWMCNT67STR _PWMCNT67;                            /* PWM Channel Counter 67 Register */
volatile PWMDTY01STR _PWMDTY01;                            /* PWM Channel Duty 01 Register */
volatile PWMDTY23STR _PWMDTY23;                            /* PWM Channel Duty 23 Register */
volatile PWMDTY45STR _PWMDTY45;                            /* PWM Channel Duty 45 Register */
volatile PWMDTY67STR _PWMDTY67;                            /* PWM Channel Duty 67 Register */
volatile PWMPER01STR _PWMPER01;                            /* PWM Channel Period 01 Register */
volatile PWMPER23STR _PWMPER23;                            /* PWM Channel Period 23 Register */
volatile PWMPER45STR _PWMPER45;                            /* PWM Channel Period 45 Register */
volatile PWMPER67STR _PWMPER67;                            /* PWM Channel Period 67 Register */
volatile SCI0BDSTR _SCI0BD;                                /* SCI 0 Baud Rate Register */
volatile SCI1BDSTR _SCI1BD;                                /* SCI 1 Baud Rate Register */
volatile TC0STR _TC0;                                      /* Timer Input Capture/Output Compare Register 0 */
volatile TC0HSTR _TC0H;                                    /* Timer Input Capture Holding Registers 0 */
volatile TC1STR _TC1;                                      /* Timer Input Capture/Output Compare Register 1 */
volatile TC1HSTR _TC1H;                                    /* Timer Input Capture Holding Registers 1 */
volatile TC2STR _TC2;                                      /* Timer Input Capture/Output Compare Register 2 */
volatile TC2HSTR _TC2H;                                    /* Timer Input Capture Holding Registers 2 */
volatile TC3STR _TC3;                                      /* Timer Input Capture/Output Compare Register 3 */
volatile TC3HSTR _TC3H;                                    /* Timer Input Capture Holding Registers 3 */
volatile TC4STR _TC4;                                      /* Timer Input Capture/Output Compare Register 4 */
volatile TC5STR _TC5;                                      /* Timer Input Capture/Output Compare Register 5 */
volatile TC6STR _TC6;                                      /* Timer Input Capture/Output Compare Register 6 */
volatile TC7STR _TC7;                                      /* Timer Input Capture/Output Compare Register 7 */
volatile TCNTSTR _TCNT;                                    /* Timer Count Register */
/*
** ###################################################################
**
**     This file was created by UNIS Processor Expert 03.33 for 
**     the Motorola HCS12 series of microcontrollers.
**
** ###################################################################
*/