io_map.c

FreeRTOSV4.1.0 安裝文件 FreeRTOS 是一个源码公开的免费的嵌入式实时操作系统

volatile CAN4IDAR1STR _CAN4IDAR1;                          /* MSCAN4 Identifier Acceptance Register 1 */
volatile CAN4IDAR2STR _CAN4IDAR2;                          /* MSCAN4 Identifier Acceptance Register 2 */
volatile CAN4IDAR3STR _CAN4IDAR3;                          /* MSCAN4 Identifier Acceptance Register 3 */
volatile CAN4IDAR4STR _CAN4IDAR4;                          /* MSCAN4 Identifier Acceptance Register 4 */
volatile CAN4IDAR5STR _CAN4IDAR5;                          /* MSCAN4 Identifier Acceptance Register 5 */
volatile CAN4IDAR6STR _CAN4IDAR6;                          /* MSCAN4 Identifier Acceptance Register 6 */
volatile CAN4IDAR7STR _CAN4IDAR7;                          /* MSCAN4 Identifier Acceptance Register 7 */
volatile CAN4IDMR0STR _CAN4IDMR0;                          /* MSCAN4 Identifier Mask Register 0 */
volatile CAN4IDMR1STR _CAN4IDMR1;                          /* MSCAN4 Identifier Mask Register 1 */
volatile CAN4IDMR2STR _CAN4IDMR2;                          /* MSCAN4 Identifier Mask Register 2 */
volatile CAN4IDMR3STR _CAN4IDMR3;                          /* MSCAN4 Identifier Mask Register 3 */
volatile CAN4IDMR4STR _CAN4IDMR4;                          /* MSCAN4 Identifier Mask Register 4 */
volatile CAN4IDMR5STR _CAN4IDMR5;                          /* MSCAN4 Identifier Mask Register 5 */
volatile CAN4IDMR6STR _CAN4IDMR6;                          /* MSCAN4 Identifier Mask Register 6 */
volatile CAN4IDMR7STR _CAN4IDMR7;                          /* MSCAN4 Identifier Mask Register 7 */
volatile CAN4RFLGSTR _CAN4RFLG;                            /* MSCAN4 Receiver Flag Register */
volatile CAN4RIERSTR _CAN4RIER;                            /* MSCAN4 Receiver Interrupt Enable Register */
volatile CAN4RXDLRSTR _CAN4RXDLR;                          /* MSCAN4 Receive Data Length Register */
volatile CAN4RXDSR0STR _CAN4RXDSR0;                        /* MSCAN4 Receive Data Segment Register 0 */
volatile CAN4RXDSR1STR _CAN4RXDSR1;                        /* MSCAN4 Receive Data Segment Register 1 */
volatile CAN4RXDSR2STR _CAN4RXDSR2;                        /* MSCAN4 Receive Data Segment Register 2 */
volatile CAN4RXDSR3STR _CAN4RXDSR3;                        /* MSCAN4 Receive Data Segment Register 3 */
volatile CAN4RXDSR4STR _CAN4RXDSR4;                        /* MSCAN4 Receive Data Segment Register 4 */
volatile CAN4RXDSR5STR _CAN4RXDSR5;                        /* MSCAN4 Receive Data Segment Register 5 */
volatile CAN4RXDSR6STR _CAN4RXDSR6;                        /* MSCAN4 Receive Data Segment Register 6 */
volatile CAN4RXDSR7STR _CAN4RXDSR7;                        /* MSCAN4 Receive Data Segment Register 7 */
volatile CAN4RXERRSTR _CAN4RXERR;                          /* MSCAN4 Receive Error Counter Register */
volatile CAN4RXIDR0STR _CAN4RXIDR0;                        /* MSCAN4 Receive Identifier Register 0 */
volatile CAN4RXIDR1STR _CAN4RXIDR1;                        /* MSCAN4 Receive Identifier Register 1 */
volatile CAN4RXIDR2STR _CAN4RXIDR2;                        /* MSCAN4 Receive Identifier Register 2 */
volatile CAN4RXIDR3STR _CAN4RXIDR3;                        /* MSCAN4 Receive Identifier Register 3 */
volatile CAN4TAAKSTR _CAN4TAAK;                            /* MSCAN4 Transmitter Message Abort Control */
volatile CAN4TARQSTR _CAN4TARQ;                            /* MSCAN 4 Transmitter Message Abort Request */
volatile CAN4TBSELSTR _CAN4TBSEL;                          /* MSCAN4 Transmit Buffer Selection */
volatile CAN4TFLGSTR _CAN4TFLG;                            /* MSCAN4 Transmitter Flag Register */
volatile CAN4TIERSTR _CAN4TIER;                            /* MSCAN4 Transmitter Interrupt Enable Register */
volatile CAN4TXDLRSTR _CAN4TXDLR;                          /* MSCAN4 Transmit Data Length Register */
volatile CAN4TXDSR0STR _CAN4TXDSR0;                        /* MSCAN4 Transmit Data Segment Register 0 */
volatile CAN4TXDSR1STR _CAN4TXDSR1;                        /* MSCAN4 Transmit Data Segment Register 1 */
volatile CAN4TXDSR2STR _CAN4TXDSR2;                        /* MSCAN4 Transmit Data Segment Register 2 */
volatile CAN4TXDSR3STR _CAN4TXDSR3;                        /* MSCAN4 Transmit Data Segment Register 3 */
volatile CAN4TXDSR4STR _CAN4TXDSR4;                        /* MSCAN4 Transmit Data Segment Register 4 */
volatile CAN4TXDSR5STR _CAN4TXDSR5;                        /* MSCAN4 Transmit Data Segment Register 5 */
volatile CAN4TXDSR6STR _CAN4TXDSR6;                        /* MSCAN4 Transmit Data Segment Register 6 */
volatile CAN4TXDSR7STR _CAN4TXDSR7;                        /* MSCAN4 Transmit Data Segment Register 7 */
volatile CAN4TXERRSTR _CAN4TXERR;                          /* MSCAN4 Transmit Error Counter Register */
volatile CAN4TXIDR0STR _CAN4TXIDR0;                        /* MSCAN4 Transmit Identifier Register 0 */
volatile CAN4TXIDR1STR _CAN4TXIDR1;                        /* MSCAN4 Transmit Identifier Register 1 */
volatile CAN4TXIDR2STR _CAN4TXIDR2;                        /* MSCAN4 Transmit Identifier Register 2 */
volatile CAN4TXIDR3STR _CAN4TXIDR3;                        /* MSCAN4 Transmit Identifier Register 3 */
volatile CAN4TXTBPRSTR _CAN4TXTBPR;                        /* MSCAN4 Transmit Transmit Buffer Priority */
volatile CFORCSTR _CFORC;                                  /* Timer Compare Force Register */
volatile CLKSELSTR _CLKSEL;                                /* CRG Clock Select Register */
volatile COPCTLSTR _COPCTL;                                /* CRG COP Control Register */
volatile CRGFLGSTR _CRGFLG;                                /* CRG Flags Register */
volatile CRGINTSTR _CRGINT;                                /* CRG Interrupt Enable Register */
volatile CTCTLSTR _CTCTL;                                  /* CRG Test Control Register */
volatile CTFLGSTR _CTFLG;                                  /* CRG Test Flags Register */
volatile DDRESTR _DDRE;                                    /* Port E Data Direction Register */
volatile DDRHSTR _DDRH;                                    /* Port H Data Direction Register */
volatile DDRJSTR _DDRJ;                                    /* Port J Data Direction Register */
volatile DDRKSTR _DDRK;                                    /* Port K Data Direction Register */
volatile DDRMSTR _DDRM;                                    /* Port M Data Direction Register */
volatile DDRPSTR _DDRP;                                    /* Port P Data Direction Register */
volatile DDRSSTR _DDRS;                                    /* Port S Data Direction Register */
volatile DDRTSTR _DDRT;                                    /* Port T Data Direction Register */
volatile DLCBARDSTR _DLCBARD;                              /* BDLC Analog Round Trip Delay Register */
volatile DLCBCR1STR _DLCBCR1;                              /* BDLC Control Register 1 */
volatile DLCBCR2STR _DLCBCR2;                              /* BDLC Control Register 2 */
volatile DLCBDRSTR _DLCBDR;                                /* BDLC Data Register */
volatile DLCBRSRSTR _DLCBRSR;                              /* BDLC Rate Select Register */
volatile DLCBSVRSTR _DLCBSVR;                              /* BDLC State Vector Register */
volatile DLCSCRSTR _DLCSCR;                                /* BDLC Control Register */
volatile DLYCTSTR _DLYCT;                                  /* Delay Counter Control Register */
volatile EBICTLSTR _EBICTL;                                /* External Bus Interface Control */
volatile ECLKDIVSTR _ECLKDIV;                              /* EEPROM Clock Divider Register */
volatile ECMDSTR _ECMD;                                    /* EEPROM Command Buffer and Register */
volatile ECNFGSTR _ECNFG;                                  /* EEPROM Configuration Register */
volatile EPROTSTR _EPROT;                                  /* EEPROM Protection Register */
volatile ESTATSTR _ESTAT;                                  /* EEPROM Status Register */
volatile FCLKDIVSTR _FCLKDIV;                              /* Flash Clock Divider Register */
volatile FCMDSTR _FCMD;                                    /* Flash Command Buffer and Register */
volatile FCNFGSTR _FCNFG;                                  /* Flash Configuration Register */
volatile FORBYPSTR _FORBYP;                                /* Crg force and bypass test register */
volatile FPROTSTR _FPROT;                                  /* Flash Protection Register */
volatile FSECSTR _FSEC;                                    /* Flash Security Register */
volatile FSTATSTR _FSTAT;                                  /* Flash Status Register */
volatile HPRIOSTR _HPRIO;                                  /* Highest Priority I Interrupt */
volatile IBADSTR _IBAD;                                    /* IIC Address Register */
volatile IBCRSTR _IBCR;                                    /* IIC Control Register */
volatile IBDRSTR _IBDR;                                    /* IIC Data I/O Register */
volatile IBFDSTR _IBFD;                                    /* IIC Frequency Divider Register */
volatile IBSRSTR _IBSR;                                    /* IIC Status Register */
volatile ICOVWSTR _ICOVW;                                  /* Input Control Overwrite Register */
volatile ICPARSTR _ICPAR;                                  /* Input Control Pulse Accumulator Register */
volatile ICSYSSTR _ICSYS;                                  /* Input Control System Control Register */
volatile INITEESTR _INITEE;                                /* Initialization of Internal EEPROM Position Register */
volatile INITRGSTR _INITRG;                                /* Initialization of Internal Register Position Register */
volatile INITRMSTR _INITRM;                                /* Initialization of Internal RAM Position Register */
volatile INTCRSTR _INTCR;                                  /* Interrupt Control Register */
volatile ITCRSTR _ITCR;                                    /* Interrupt Test Control Register */
volatile ITESTSTR _ITEST;                                  /* Interrupt Test Register */
volatile MCCTLSTR _MCCTL;                                  /* Modulus Down Counter underflow */
volatile MCFLGSTR _MCFLG;                                  /* 16-Bit Modulus Down Counter Flag Register */
volatile MEMSIZ0STR _MEMSIZ0;                              /* Memory Size Register Zero */
volatile MEMSIZ1STR _MEMSIZ1;                              /* Memory Size Register One */
volatile MISCSTR _MISC;                                    /* Miscellaneous Mapping Control Register */
volatile MODESTR _MODE;                                    /* Mode Register */
volatile MODRRSTR _MODRR;                                  /* Module Routing Register */
volatile MTST0STR _MTST0;                                  /* MTST0 */
volatile MTST1STR _MTST1;                                  /* MTST1 */
volatile OC7DSTR _OC7D;                                    /* Output Compare 7 Data Register */
volatile OC7MSTR _OC7M;                                    /* Output Compare 7 Mask Register */
volatile PACTLSTR _PACTL;                                  /* 16-Bit Pulse Accumulator A Control Register */
volatile PAFLGSTR _PAFLG;                                  /* Pulse Accumulator A Flag Register */
volatile PARTIDHSTR _PARTIDH;                              /* Part ID Register High */
volatile PARTIDLSTR _PARTIDL;                              /* Part ID Register Low */
volatile PBCTLSTR _PBCTL;                                  /* 16-Bit Pulse Accumulator B Control Register */
volatile PBFLGSTR _PBFLG;                                  /* Pulse Accumulator B Flag Register */
volatile PEARSTR _PEAR;                                    /* Port E Assignment Register */
volatile PERHSTR _PERH;                                    /* Port H Pull Device Enable Register */
volatile PERJSTR _PERJ;                                    /* Port J Pull Device Enable Register */
volatile PERMSTR _PERM;                                    /* Port M Pull Device Enable Register */
volatile PERPSTR _PERP;                                    /* Port P Pull Device Enable Register */
volatile PERSSTR _PERS;                                    /* Port S Pull Device Enable Register */
volatile PERTSTR _PERT;                                    /* Port T Pull Device Enable Register */
volatile PIEHSTR _PIEH;                                    /* Port H Interrupt Enable Register */
volatile PIEJSTR _PIEJ;                                    /* Port J Interrupt Enable Register */
volatile PIEPSTR _PIEP;                                    /* Port P Interrupt Enable Register */
volatile PIFHSTR _PIFH;                                    /* Port H Interrupt Flag Register */
volatile PIFJSTR _PIFJ;                                    /* Port J Interrupt Flag Register */
volatile PIFPSTR _PIFP;                                    /* Port P Interrupt Flag Register */
volatile PLLCTLSTR _PLLCTL;                                /* CRG PLL Control Register */
volatile PORTAD0STR _PORTAD0;                              /* Port AD0 Register */
volatile PORTAD1STR _PORTAD1;                              /* Port AD1 Register */
volatile PORTESTR _PORTE;                                  /* Port E Register */
volatile PORTKSTR _PORTK;                                  /* Port K Data Register */
volatile PPAGESTR _PPAGE;                                  /* Page Index Register */
volatile PPSHSTR _PPSH;                                    /* Port H Polarity Select Register */
volatile PPSJSTR _PPSJ;                                    /* PortJP Polarity Select Register */