io_map.c

FreeRTOSV4.1.0 安裝文件 FreeRTOS 是一个源码公开的免费的嵌入式实时操作系统

/** ###################################################################
**     THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**     Filename  : IO_Map.C
**     Project   : RTOSDemo
**     Processor : MC9S12C32CFU
**     Beantype  : IO_Map
**     Version   : Driver 01.01
**     Compiler  : Metrowerks HC12 C Compiler
**     Date/Time : 10/05/2005, 11:11
**     Abstract  :
**         This bean "IO_Map" implements an IO devices mapping.
**     Settings  :
**
**     Contents  :
**         No public methods
**
**     (c) Copyright UNIS, spol. s r.o. 1997-2002
**     UNIS, spol. s r.o.
**     Jundrovska 33
**     624 00 Brno
**     Czech Republic
**     http      : www.processorexpert.com
**     mail      : [e-mail]
** ###################################################################*/
/* Based on CPU DB MC9S12C32_80, version 2.87.264 */
#include "PE_types.h"
#include "IO_Map.h"

volatile ARMCOPSTR _ARMCOP;                                /* CRG COP Timer Arm/Reset Register */
volatile ATDDIENSTR _ATDDIEN;                              /* ATD Input Enable Mask Register */
volatile ATDSTAT0STR _ATDSTAT0;                            /* A/D Status Register 0 */
volatile ATDSTAT1STR _ATDSTAT1;                            /* A/D Status Register 1 */
volatile BDMCCRSTR _BDMCCR;                                /* BDM CCR Holding Register */
volatile BDMINRSTR _BDMINR;                                /* BDM Internal Register Position Register */
volatile BDMSTSSTR _BDMSTS;                                /* BDM Status Register */
volatile BKP0HSTR _BKP0H;                                  /* First Address High Byte Breakpoint Register */
volatile BKP0LSTR _BKP0L;                                  /* First Address Low Byte Breakpoint Register */
volatile BKP0XSTR _BKP0X;                                  /* First Address Memory Expansion Breakpoint Register */
volatile BKP1HSTR _BKP1H;                                  /* Data (Second Address) High Byte Breakpoint Register */
volatile BKP1LSTR _BKP1L;                                  /* Data (Second Address) Low Byte Breakpoint Register */
volatile BKP1XSTR _BKP1X;                                  /* Second Address Memory Expansion Breakpoint Register */
volatile BKPCT0STR _BKPCT0;                                /* Breakpoint Control Register 0 */
volatile BKPCT1STR _BKPCT1;                                /* Breakpoint Control Register 1 */
volatile CANBTR0STR _CANBTR0;                              /* MSCAN Bus Timing Register 0 */
volatile CANBTR1STR _CANBTR1;                              /* MSCAN Bus Timing Register 1 */
volatile CANCTL0STR _CANCTL0;                              /* MSCAN Control 0 Register */
volatile CANCTL1STR _CANCTL1;                              /* MSCAN Control 1 Register */
volatile CANIDACSTR _CANIDAC;                              /* MSCAN Identifier Acceptance Control Register */
volatile CANIDAR0STR _CANIDAR0;                            /* MSCAN Identifier Acceptance Register 0 */
volatile CANIDAR1STR _CANIDAR1;                            /* MSCAN Identifier Acceptance Register 1 */
volatile CANIDAR2STR _CANIDAR2;                            /* MSCAN Identifier Acceptance Register 2 */
volatile CANIDAR3STR _CANIDAR3;                            /* MSCAN Identifier Acceptance Register 3 */
volatile CANIDAR4STR _CANIDAR4;                            /* MSCAN Identifier Acceptance Register 4 */
volatile CANIDAR5STR _CANIDAR5;                            /* MSCAN Identifier Acceptance Register 5 */
volatile CANIDAR6STR _CANIDAR6;                            /* MSCAN Identifier Acceptance Register 6 */
volatile CANIDAR7STR _CANIDAR7;                            /* MSCAN Identifier Acceptance Register 7 */
volatile CANIDMR0STR _CANIDMR0;                            /* MSCAN Identifier Mask Register 0 */
volatile CANIDMR1STR _CANIDMR1;                            /* MSCAN Identifier Mask Register 1 */
volatile CANIDMR2STR _CANIDMR2;                            /* MSCAN Identifier Mask Register 2 */
volatile CANIDMR3STR _CANIDMR3;                            /* MSCAN Identifier Mask Register 3 */
volatile CANIDMR4STR _CANIDMR4;                            /* MSCAN Identifier Mask Register 4 */
volatile CANIDMR5STR _CANIDMR5;                            /* MSCAN Identifier Mask Register 5 */
volatile CANIDMR6STR _CANIDMR6;                            /* MSCAN Identifier Mask Register 6 */
volatile CANIDMR7STR _CANIDMR7;                            /* MSCAN Identifier Mask Register 7 */
volatile CANRFLGSTR _CANRFLG;                              /* MSCAN Receiver Flag Register */
volatile CANRIERSTR _CANRIER;                              /* MSCAN Receiver Interrupt Enable Register */
volatile CANRXDLRSTR _CANRXDLR;                            /* MSCAN Receive Data Length Register */
volatile CANRXDSR0STR _CANRXDSR0;                          /* MSCAN Receive Data Segment Register 0 */
volatile CANRXDSR1STR _CANRXDSR1;                          /* MSCAN Receive Data Segment Register 1 */
volatile CANRXDSR2STR _CANRXDSR2;                          /* MSCAN Receive Data Segment Register 2 */
volatile CANRXDSR3STR _CANRXDSR3;                          /* MSCAN Receive Data Segment Register 3 */
volatile CANRXDSR4STR _CANRXDSR4;                          /* MSCAN Receive Data Segment Register 4 */
volatile CANRXDSR5STR _CANRXDSR5;                          /* MSCAN Receive Data Segment Register 5 */
volatile CANRXDSR6STR _CANRXDSR6;                          /* MSCAN Receive Data Segment Register 6 */
volatile CANRXDSR7STR _CANRXDSR7;                          /* MSCAN Receive Data Segment Register 7 */
volatile CANRXERRSTR _CANRXERR;                            /* MSCAN Receive Error Counter Register */
volatile CANRXIDR0STR _CANRXIDR0;                          /* MSCAN Receive Identifier Register 0 */
volatile CANRXIDR1STR _CANRXIDR1;                          /* MSCAN Receive Identifier Register 1 */
volatile CANRXIDR2STR _CANRXIDR2;                          /* MSCAN Receive Identifier Register 2 */
volatile CANRXIDR3STR _CANRXIDR3;                          /* MSCAN Receive Identifier Register 3 */
volatile CANTAAKSTR _CANTAAK;                              /* MSCAN Transmitter Message Abort Control */
volatile CANTARQSTR _CANTARQ;                              /* MSCAN Transmitter Message Abort Request */
volatile CANTBSELSTR _CANTBSEL;                            /* MSCAN Transmit Buffer Selection */
volatile CANTFLGSTR _CANTFLG;                              /* MSCAN Transmitter Flag Register */
volatile CANTIERSTR _CANTIER;                              /* MSCAN Transmitter Interrupt Enable Register */
volatile CANTXDLRSTR _CANTXDLR;                            /* MSCAN Transmit Data Length Register */
volatile CANTXDSR0STR _CANTXDSR0;                          /* MSCAN Transmit Data Segment Register 0 */
volatile CANTXDSR1STR _CANTXDSR1;                          /* MSCAN Transmit Data Segment Register 1 */
volatile CANTXDSR2STR _CANTXDSR2;                          /* MSCAN Transmit Data Segment Register 2 */
volatile CANTXDSR3STR _CANTXDSR3;                          /* MSCAN Transmit Data Segment Register 3 */
volatile CANTXDSR4STR _CANTXDSR4;                          /* MSCAN Transmit Data Segment Register 4 */
volatile CANTXDSR5STR _CANTXDSR5;                          /* MSCAN Transmit Data Segment Register 5 */
volatile CANTXDSR6STR _CANTXDSR6;                          /* MSCAN Transmit Data Segment Register 6 */
volatile CANTXDSR7STR _CANTXDSR7;                          /* MSCAN Transmit Data Segment Register 7 */
volatile CANTXERRSTR _CANTXERR;                            /* MSCAN Transmit Error Counter Register */
volatile CANTXIDR0STR _CANTXIDR0;                          /* MSCAN Transmit Identifier Register 0 */
volatile CANTXIDR1STR _CANTXIDR1;                          /* MSCAN Transmit Identifier Register 1 */
volatile CANTXIDR2STR _CANTXIDR2;                          /* MSCAN Transmit Identifier Register 2 */
volatile CANTXIDR3STR _CANTXIDR3;                          /* MSCAN Transmit Identifier Register 3 */
volatile CANTXTBPRSTR _CANTXTBPR;                          /* MSCAN Transmit Buffer Priority */
volatile CFORCSTR _CFORC;                                  /* Timer Compare Force Register */
volatile CLKSELSTR _CLKSEL;                                /* CRG Clock Select Register */
volatile COPCTLSTR _COPCTL;                                /* CRG COP Control Register */
volatile CRGFLGSTR _CRGFLG;                                /* CRG Flags Register */
volatile CRGINTSTR _CRGINT;                                /* CRG Interrupt Enable Register */
volatile CTCTLSTR _CTCTL;                                  /* CRG Test Control Register */
volatile CTFLGSTR _CTFLG;                                  /* CRG Test Flags Register */
volatile DDRADSTR _DDRAD;                                  /* Port AD Data Direction Register */
volatile DDRESTR _DDRE;                                    /* Port E Data Direction Register */
volatile DDRJSTR _DDRJ;                                    /* Port J Data Direction Register */
volatile DDRKSTR _DDRK;                                    /* Port K Data Direction Register */
volatile DDRMSTR _DDRM;                                    /* Port M Data Direction Register */
volatile DDRPSTR _DDRP;                                    /* Port P Data Direction Register */
volatile DDRSSTR _DDRS;                                    /* Port S Data Direction Register */
volatile DDRTSTR _DDRT;                                    /* Port T Data Direction Register */
volatile EBICTLSTR _EBICTL;                                /* External Bus Interface Control */
volatile FCLKDIVSTR _FCLKDIV;                              /* Flash Clock Divider Register */
volatile FCMDSTR _FCMD;                                    /* Flash Command Buffer and Register */
volatile FCNFGSTR _FCNFG;                                  /* Flash Configuration Register */
volatile FPROTSTR _FPROT;                                  /* Flash Protection Register */
volatile FSECSTR _FSEC;                                    /* Flash Security Register */
volatile FSTATSTR _FSTAT;                                  /* Flash Status Register */
volatile HPRIOSTR _HPRIO;                                  /* Highest Priority I Interrupt */
volatile INITEESTR _INITEE;                                /* Initialization of Internal EEPROM Position Register */
volatile INITRGSTR _INITRG;                                /* Initialization of Internal Register Position Register */
volatile INITRMSTR _INITRM;                                /* Initialization of Internal RAM Position Register */
volatile INTCRSTR _INTCR;                                  /* Interrupt Control Register */
volatile ITCRSTR _ITCR;                                    /* Interrupt Test Control Register */
volatile ITESTSTR _ITEST;                                  /* Interrupt Test Register */
volatile MEMSIZ0STR _MEMSIZ0;                              /* Memory Size Register Zero */
volatile MEMSIZ1STR _MEMSIZ1;                              /* Memory Size Register One */