📄 at91sam7s64_inc.h
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#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected
#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Reset Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_RSTC structure ***
#define RSTC_RCR ( 0) // Reset Control Register
#define RSTC_RSR ( 4) // Reset Status Register
#define RSTC_RMR ( 8) // Reset Mode Register
// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
#define AT91C_SYSC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
#define AT91C_SYSC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset
#define AT91C_SYSC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
#define AT91C_SYSC_EXTRST (0x1 << 3) // (RSTC) External Reset
#define AT91C_SYSC_KEY (0xFF << 24) // (RSTC) Password
// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
#define AT91C_SYSC_URSTS (0x1 << 0) // (RSTC) User Reset Status
#define AT91C_SYSC_BODSTS (0x1 << 1) // (RSTC) Brown-out Detection Status
#define AT91C_SYSC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
#define AT91C_SYSC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
#define AT91C_SYSC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
#define AT91C_SYSC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
#define AT91C_SYSC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
#define AT91C_SYSC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brown-out Reset.
#define AT91C_SYSC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
#define AT91C_SYSC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
#define AT91C_SYSC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
#define AT91C_SYSC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
#define AT91C_SYSC_ERSTL (0xF << 8) // (RSTC) User Reset Enable
#define AT91C_SYSC_BODIEN (0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_RTTC structure ***
#define RTTC_RTMR ( 0) // Real-time Mode Register
#define RTTC_RTAR ( 4) // Real-time Alarm Register
#define RTTC_RTVR ( 8) // Real-time Value Register
#define RTTC_RTSR (12) // Real-time Status Register
// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
#define AT91C_SYSC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
#define AT91C_SYSC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
#define AT91C_SYSC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
#define AT91C_SYSC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
#define AT91C_SYSC_ALMV (0x0 << 0) // (RTTC) Alarm Value
// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
#define AT91C_SYSC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
#define AT91C_SYSC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
#define AT91C_SYSC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_PITC structure ***
#define PITC_PIMR ( 0) // Period Interval Mode Register
#define PITC_PISR ( 4) // Period Interval Status Register
#define PITC_PIVR ( 8) // Period Interval Value Register
#define PITC_PIIR (12) // Period Interval Image Register
// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
#define AT91C_SYSC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
#define AT91C_SYSC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
#define AT91C_SYSC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
#define AT91C_SYSC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
#define AT91C_SYSC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
#define AT91C_SYSC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_WDTC structure ***
#define WDTC_WDCR ( 0) // Watchdog Control Register
#define WDTC_WDMR ( 4) // Watchdog Mode Register
#define WDTC_WDSR ( 8) // Watchdog Status Register
// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
#define AT91C_SYSC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
#define AT91C_SYSC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
#define AT91C_SYSC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
#define AT91C_SYSC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
#define AT91C_SYSC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
#define AT91C_SYSC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
#define AT91C_SYSC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
#define AT91C_SYSC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
#define AT91C_SYSC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
#define AT91C_SYSC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
#define AT91C_SYSC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Memory Controller Interface
// *****************************************************************************
// *** Register offset in AT91S_MC structure ***
#define MC_RCR ( 0) // MC Remap Control Register
#define MC_ASR ( 4) // MC Abort Status Register
#define MC_AASR ( 8) // MC Abort Address Status Register
#define MC_FMR (96) // MC Flash Mode Register
#define MC_FCR (100) // MC Flash Command Register
#define MC_FSR (104) // MC Flash Status Register
// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit
// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status
#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status
#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status
#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte
#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word
#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word
#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status
#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read
#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write
#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch
#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source
#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source
#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source
#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source
// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready
#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error
#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error
#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming
#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State
#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number
// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command
#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits.
#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits.
#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit.
#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number
#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key
// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status
#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status
#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status
#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status
#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status
#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status
#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status
#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status
#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status
#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status
#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status
#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status
#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status
#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status
#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status
#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status
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