at91sam7s64_inc.h

FreeRTOSV4.1.0 安裝文件 FreeRTOS 是一个源码公开的免费的嵌入式实时操作系统

// ----------------------------------------------------------------------------
//          ATMEL Microcontroller Software Support  -  ROUSSET  -
// ----------------------------------------------------------------------------
//  The software is delivered "AS IS" without warranty or condition of any
//  kind, either express, implied or statutory. This includes without
//  limitation any warranty or condition with respect to merchantability or
//  fitness for any particular purpose, or against the infringements of
//  intellectual property rights of others.
// ----------------------------------------------------------------------------
// File Name           : AT91SAM7S64.h
// Object              : AT91SAM7S64 definitions
// Generated           : AT91 SW Application Group  07/16/2004 (07:43:09)
// 
// CVS Reference       : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004//
// CVS Reference       : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004//
// CVS Reference       : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004//
// CVS Reference       : /UDP_1765B.pl/1.3/Fri Aug  2 14:45:38 2002//
// CVS Reference       : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
// CVS Reference       : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//
// CVS Reference       : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
// CVS Reference       : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//
// CVS Reference       : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004//
// CVS Reference       : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003//
// CVS Reference       : /SSC_1762A.pl/1.2/Fri Nov  8 13:26:40 2002//
// CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
// CVS Reference       : /TWI_1761B.pl/1.4/Fri Feb  7 10:30:08 2003//
// CVS Reference       : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002//
// CVS Reference       : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003//
// CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
// ----------------------------------------------------------------------------

// Hardware register definition

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR System Peripherals
// *****************************************************************************
// *** Register offset in AT91S_SYSC structure ***
#define SYSC_AIC_SMR    ( 0) // Source Mode Register
#define SYSC_AIC_SVR    (128) // Source Vector Register
#define SYSC_AIC_IVR    (256) // IRQ Vector Register
#define SYSC_AIC_FVR    (260) // FIQ Vector Register
#define SYSC_AIC_ISR    (264) // Interrupt Status Register
#define SYSC_AIC_IPR    (268) // Interrupt Pending Register
#define SYSC_AIC_IMR    (272) // Interrupt Mask Register
#define SYSC_AIC_CISR   (276) // Core Interrupt Status Register
#define SYSC_AIC_IECR   (288) // Interrupt Enable Command Register
#define SYSC_AIC_IDCR   (292) // Interrupt Disable Command Register
#define SYSC_AIC_ICCR   (296) // Interrupt Clear Command Register
#define SYSC_AIC_ISCR   (300) // Interrupt Set Command Register
#define SYSC_AIC_EOICR  (304) // End of Interrupt Command Register
#define SYSC_AIC_SPU    (308) // Spurious Vector Register
#define SYSC_AIC_DCR    (312) // Debug Control Register (Protect)
#define SYSC_AIC_FFER   (320) // Fast Forcing Enable Register
#define SYSC_AIC_FFDR   (324) // Fast Forcing Disable Register
#define SYSC_AIC_FFSR   (328) // Fast Forcing Status Register
#define SYSC_DBGU_CR    (512) // Control Register
#define SYSC_DBGU_MR    (516) // Mode Register
#define SYSC_DBGU_IER   (520) // Interrupt Enable Register
#define SYSC_DBGU_IDR   (524) // Interrupt Disable Register
#define SYSC_DBGU_IMR   (528) // Interrupt Mask Register
#define SYSC_DBGU_CSR   (532) // Channel Status Register
#define SYSC_DBGU_RHR   (536) // Receiver Holding Register
#define SYSC_DBGU_THR   (540) // Transmitter Holding Register
#define SYSC_DBGU_BRGR  (544) // Baud Rate Generator Register
#define SYSC_DBGU_C1R   (576) // Chip ID1 Register
#define SYSC_DBGU_C2R   (580) // Chip ID2 Register
#define SYSC_DBGU_FNTR  (584) // Force NTRST Register
#define SYSC_DBGU_RPR   (768) // Receive Pointer Register
#define SYSC_DBGU_RCR   (772) // Receive Counter Register
#define SYSC_DBGU_TPR   (776) // Transmit Pointer Register
#define SYSC_DBGU_TCR   (780) // Transmit Counter Register
#define SYSC_DBGU_RNPR  (784) // Receive Next Pointer Register
#define SYSC_DBGU_RNCR  (788) // Receive Next Counter Register
#define SYSC_DBGU_TNPR  (792) // Transmit Next Pointer Register
#define SYSC_DBGU_TNCR  (796) // Transmit Next Counter Register
#define SYSC_DBGU_PTCR  (800) // PDC Transfer Control Register
#define SYSC_DBGU_PTSR  (804) // PDC Transfer Status Register
#define SYSC_PIOA_PER   (1024) // PIO Enable Register
#define SYSC_PIOA_PDR   (1028) // PIO Disable Register
#define SYSC_PIOA_PSR   (1032) // PIO Status Register
#define SYSC_PIOA_OER   (1040) // Output Enable Register
#define SYSC_PIOA_ODR   (1044) // Output Disable Registerr
#define SYSC_PIOA_OSR   (1048) // Output Status Register
#define SYSC_PIOA_IFER  (1056) // Input Filter Enable Register
#define SYSC_PIOA_IFDR  (1060) // Input Filter Disable Register
#define SYSC_PIOA_IFSR  (1064) // Input Filter Status Register
#define SYSC_PIOA_SODR  (1072) // Set Output Data Register
#define SYSC_PIOA_CODR  (1076) // Clear Output Data Register
#define SYSC_PIOA_ODSR  (1080) // Output Data Status Register
#define SYSC_PIOA_PDSR  (1084) // Pin Data Status Register
#define SYSC_PIOA_IER   (1088) // Interrupt Enable Register
#define SYSC_PIOA_IDR   (1092) // Interrupt Disable Register
#define SYSC_PIOA_IMR   (1096) // Interrupt Mask Register
#define SYSC_PIOA_ISR   (1100) // Interrupt Status Register
#define SYSC_PIOA_MDER  (1104) // Multi-driver Enable Register
#define SYSC_PIOA_MDDR  (1108) // Multi-driver Disable Register
#define SYSC_PIOA_MDSR  (1112) // Multi-driver Status Register
#define SYSC_PIOA_PPUDR (1120) // Pull-up Disable Register
#define SYSC_PIOA_PPUER (1124) // Pull-up Enable Register
#define SYSC_PIOA_PPUSR (1128) // Pad Pull-up Status Register
#define SYSC_PIOA_ASR   (1136) // Select A Register
#define SYSC_PIOA_BSR   (1140) // Select B Register
#define SYSC_PIOA_ABSR  (1144) // AB Select Status Register
#define SYSC_PIOA_OWER  (1184) // Output Write Enable Register
#define SYSC_PIOA_OWDR  (1188) // Output Write Disable Register
#define SYSC_PIOA_OWSR  (1192) // Output Write Status Register
#define SYSC_PMC_SCER   (3072) // System Clock Enable Register
#define SYSC_PMC_SCDR   (3076) // System Clock Disable Register
#define SYSC_PMC_SCSR   (3080) // System Clock Status Register
#define SYSC_PMC_PCER   (3088) // Peripheral Clock Enable Register
#define SYSC_PMC_PCDR   (3092) // Peripheral Clock Disable Register
#define SYSC_PMC_PCSR   (3096) // Peripheral Clock Status Register
#define SYSC_PMC_MOR    (3104) // Main Oscillator Register
#define SYSC_PMC_MCFR   (3108) // Main Clock  Frequency Register
#define SYSC_PMC_PLLR   (3116) // PLL Register
#define SYSC_PMC_MCKR   (3120) // Master Clock Register
#define SYSC_PMC_PCKR   (3136) // Programmable Clock Register
#define SYSC_PMC_IER    (3168) // Interrupt Enable Register
#define SYSC_PMC_IDR    (3172) // Interrupt Disable Register
#define SYSC_PMC_SR     (3176) // Status Register
#define SYSC_PMC_IMR    (3180) // Interrupt Mask Register
#define SYSC_RSTC_RCR   (3328) // Reset Control Register
#define SYSC_RSTC_RSR   (3332) // Reset Status Register
#define SYSC_RSTC_RMR   (3336) // Reset Mode Register
#define SYSC_RTTC_RTMR  (3360) // Real-time Mode Register
#define SYSC_RTTC_RTAR  (3364) // Real-time Alarm Register
#define SYSC_RTTC_RTVR  (3368) // Real-time Value Register
#define SYSC_RTTC_RTSR  (3372) // Real-time Status Register
#define SYSC_PITC_PIMR  (3376) // Period Interval Mode Register
#define SYSC_PITC_PISR  (3380) // Period Interval Status Register
#define SYSC_PITC_PIVR  (3384) // Period Interval Value Register
#define SYSC_PITC_PIIR  (3388) // Period Interval Image Register
#define SYSC_WDTC_WDCR  (3392) // Watchdog Control Register
#define SYSC_WDTC_WDMR  (3396) // Watchdog Mode Register
#define SYSC_WDTC_WDSR  (3400) // Watchdog Status Register
#define SYSC_SYSC_VRPM  (3424) // Voltage Regulator Power Mode Register
// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- 
#define AT91C_SYSC_PSTDBY         (0x1 <<  0) // (SYSC) Voltage Regulator Power Mode

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
// *****************************************************************************
// *** Register offset in AT91S_AIC structure ***
#define AIC_SMR         ( 0) // Source Mode Register
#define AIC_SVR         (128) // Source Vector Register
#define AIC_IVR         (256) // IRQ Vector Register
#define AIC_FVR         (260) // FIQ Vector Register
#define AIC_ISR         (264) // Interrupt Status Register
#define AIC_IPR         (268) // Interrupt Pending Register
#define AIC_IMR         (272) // Interrupt Mask Register
#define AIC_CISR        (276) // Core Interrupt Status Register
#define AIC_IECR        (288) // Interrupt Enable Command Register
#define AIC_IDCR        (292) // Interrupt Disable Command Register
#define AIC_ICCR        (296) // Interrupt Clear Command Register
#define AIC_ISCR        (300) // Interrupt Set Command Register
#define AIC_EOICR       (304) // End of Interrupt Command Register
#define AIC_SPU         (308) // Spurious Vector Register
#define AIC_DCR         (312) // Debug Control Register (Protect)
#define AIC_FFER        (320) // Fast Forcing Enable Register
#define AIC_FFDR        (324) // Fast Forcing Disable Register
#define AIC_FFSR        (328) // Fast Forcing Status Register
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
#define AT91C_AIC_PRIOR           (0x7 <<  0) // (AIC) Priority Level
#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
#define AT91C_AIC_SRCTYPE         (0x3 <<  5) // (AIC) Interrupt Source Type
#define 	AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  (0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive
#define 	AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   (0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered
#define 	AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       (0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive
#define 	AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    (0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
#define AT91C_AIC_NFIQ            (0x1 <<  0) // (AIC) NFIQ Status
#define AT91C_AIC_NIRQ            (0x1 <<  1) // (AIC) NIRQ Status
// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
#define AT91C_AIC_DCR_PROT        (0x1 <<  0) // (AIC) Protection Mode
#define AT91C_AIC_DCR_GMSK        (0x1 <<  1) // (AIC) General Mask

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Debug Unit
// *****************************************************************************
// *** Register offset in AT91S_DBGU structure ***