clk.doc

这是用AHDL语言即abel语言编写的逻辑可编程器件原代码！供大家参考！

                                                                      Page 1
ABEL 4.00  -  Device Utilization Chart         Sun Jul 17 22:31:17 19:5

for example

    ==== P16V8R Programmed Logic ====


Q0.D   = (  Q0 ); " ISTYPE 'INVERT'
Q0.C   = (  CLK );




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ABEL 4.00  -  Device Utilization Chart         Sun Jul 17 22:31:17 19:5

for example

                 ==== P16V8R Chip Diagram ====



                            P16V8R

                 +---------\       /---------+
                 |          \     /          |
                 |           -----           |
             CLK |  1                    20  | Vcc             
                 |                           |
                 |  2                    19  |                 
                 |                           |
                 |  3                    18  |                 
                 |                           |
                 |  4                    17  |                 
                 |                           |
                 |  5                    16  |                 
                 |                           |
                 |  6                    15  |                 
                 |                           |
                 |  7                    14  |                 
                 |                           |
                 |  8                    13  | Q0              
                 |                           |
                 |  9                    12  |                 
                 |                           |
             GND | 10                    11  |                 
                 |                           |
                 |                           |
                 `---------------------------'

                SIGNATURE: N/A


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ABEL 4.00  -  Device Utilization Chart         Sun Jul 17 22:31:17 19:5

for example

                ==== P16V8R Resource Allocations ====


        Device        | Resource  |   Design    |    Part     |  
       Resources      | Available | Requirement | Utilization | Unused
======================|===========|=============|=============|==============
                      |           |             |             |
Dedicated input pins  |      8    |       1     |     0       |     8 (100 %)
Combinatorial inputs  |      8    |       0     |     0       |     8 (100 %)
Registered inputs     |      -    |       0     |     -       |     -
                      |           |             |             |
Dedicated output pins |      -    |       0     |     -       |     -
Bidirectional pins    |      8    |       1     |     1       |     7 ( 87 %)
Combinatorial outputs |      -    |       0     |     -       |     -
Registered outputs    |      -    |       1     |     -       |     -
Reg/Com outputs       |      8    |       -     |     1       |     7 ( 87 %)
Two-input XOR         |      -    |       0     |     -       |     -
                      |           |             |             |
Buried nodes          |      -    |       0     |     -       |     -
Buried registers      |      -    |       0     |     -       |     -
Buried combinatorials |      -    |       0     |     -       |     -



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ABEL 4.00  -  Device Utilization Chart         Sun Jul 17 22:31:17 19:5

for example

                ==== P16V8R Product Terms Distribution ====


            Signal             |    Pin   | Terms | Terms | Terms
             Name              | Assigned | Used  |  Max  | Unused
===============================|==========|=======|=======|=======
Q0.REG                         |   13     |   1   |   8   |   7


     ==== List of Inputs/Feedbacks ====

Signal Name                    | Pin      | Pin Type
============================== |==========|=========
CLK                            |    1     | CLK
Q0                             |   13     | BIDIR



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ABEL 4.00  -  Device Utilization Chart         Sun Jul 17 22:31:17 19:5

for example

    ==== P16V8R Unused Resources ====


 Pin   |  Pin   |   Product   | Flip-flop
Number |  Type  |   Terms     |   Type
=======|========|=============|==========
    2  |  INPUT |      -      |    -   
    3  |  INPUT |      -      |    -   
    4  |  INPUT |      -      |    -   
    5  |  INPUT |      -      |    -   
    6  |  INPUT |      -      |    -   
    7  |  INPUT |      -      |    -   
    8  |  INPUT |      -      |    -   
    9  |  INPUT |      -      |    -   
   12  |  BIDIR | NORMAL  7   |    D
   14  |  BIDIR | NORMAL  7   |    D
   15  |  BIDIR | NORMAL  7   |    D
   16  |  BIDIR | NORMAL  7   |    D
   17  |  BIDIR | NORMAL  7   |    D
   18  |  BIDIR | NORMAL  7   |    D
   19  |  BIDIR | NORMAL  7   |    D



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ABEL 4.00  -  Device Utilization Chart         Sun Jul 17 22:31:17 19:5

for example

    ==== I/O Files ====


Module: 'clk'


Input files
===========
ABEL PLA file: clk.tt2
Vector file: clk.tmv
Device library: P16V8R.dev

Output files
============
Report file: clk.doc
Programmer load file: clk.jed