__projnav.log

基于FPGA的can 总线设计

    Found 10-bit subtractor for signal <$n0000> created at line 204.
    Found 9-bit subtractor for signal <$n0003> created at line 307.
    Found 11-bit comparator equal for signal <$n0007> created at line 204.
    Found 8-bit comparator greater for signal <$n0030> created at line 300.
    Found 8-bit comparator equal for signal <$n0034> created at line 226.
    Found 8-bit comparator equal for signal <$n0035> created at line 224.
    Found 4-bit adder for signal <$n0038> created at line 300.
    Found 8-bit comparator not equal for signal <$n0041> created at line 331.
    Found 8-bit comparator not equal for signal <$n0042> created at line 357.
    Found 2-bit adder carry out for signal <$n0043> created at line 300.
    Found 4-bit adder carry out for signal <$n0044> created at line 331.
    Found 6-bit adder carry out for signal <$n0045> created at line 194.
    Found 9-bit up counter for signal <clk_cnt>.
    Found 4-bit register for signal <delay>.
    Found 8-bit up counter for signal <quant_cnt>.
    Found 1-bit register for signal <resync_blocked>.
    Found 1-bit register for signal <resync_latched>.
    Found 2-bit register for signal <sample>.
    Found 1-bit register for signal <seg1>.
    Found 1-bit register for signal <seg2>.
    Found 1-bit register for signal <sync>.
    Found 1-bit register for signal <sync_blocked>.
    Found 10-bit comparator less for signal <sync_window>.
    Found 1 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   2 Counter(s).
	inferred  16 D-type flip-flop(s).
	inferred   6 Adder/Subtracter(s).
	inferred   7 Comparator(s).
	inferred   1 Multiplexer(s).
Unit <can_btl> synthesized.


Synthesizing Unit <can_registers>.
    Related source file is can_registers.v.
WARNING:Xst:646 - Signal <info_empty_q> is assigned but never used.
    Found 8-bit register for signal <data_out>.
    Found 1-bit register for signal <single_shot_transmission>.
    Found 3-bit comparator equal for signal <$n0015> created at line 748.
    Found 1-bit xor2 for signal <$n0178> created at line 1143.
    Found 1-bit xor2 for signal <$n0179> created at line 1143.
    Found 1-bit register for signal <arbitration_lost_irq>.
    Found 1-bit register for signal <bus_error_irq>.
    Found 3-bit up counter for signal <clkout_cnt>.
    Found 1-bit register for signal <clkout_tmp>.
    Found 1-bit register for signal <data_overrun_irq>.
    Found 1-bit register for signal <error_irq>.
    Found 1-bit register for signal <error_passive_irq>.
    Found 1-bit register for signal <error_status_q>.
    Found 1-bit register for signal <node_bus_off_q>.
    Found 1-bit register for signal <node_error_passive_q>.
    Found 1-bit register for signal <overrun_q>.
    Found 1-bit register for signal <overrun_status>.
    Found 1-bit register for signal <receive_buffer_status>.
    Found 1-bit register for signal <receive_irq>.
    Found 1-bit register for signal <transmission_complete>.
    Found 1-bit register for signal <transmit_buffer_status>.
    Found 1-bit register for signal <transmit_buffer_status_q>.
    Found 1-bit register for signal <transmit_irq>.
    Found 1-bit register for signal <tx_successful_q>.
    Found 4 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Counter(s).
	inferred  27 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   4 Multiplexer(s).
Unit <can_registers> synthesized.


Synthesizing Unit <can_top>.
    Related source file is can_top.v.
WARNING:Xst:646 - Signal <clk_en> is assigned but never used.
WARNING:Xst:646 - Signal <tx_err_cnt_dummy> is assigned but never used.
WARNING:Xst:646 - Signal <resync> is assigned but never used.
WARNING:Xst:646 - Signal <rx_err_cnt_dummy> is assigned but never used.
    Found 1-bit tristate buffer for signal <tx_o>.
    Found 8-bit tristate buffer for signal <port_0_io>.
    Found 8-bit comparator greatequal for signal <$n0005> created at line 636.
    Found 8-bit comparator lessequal for signal <$n0006> created at line 636.
    Found 8-bit comparator greatequal for signal <$n0007> created at line 636.
    Found 8-bit comparator lessequal for signal <$n0008> created at line 636.
    Found 8-bit register for signal <addr_latched>.
    Found 8-bit register for signal <data_out>.
    Found 1-bit register for signal <rd_i_q>.
    Found 1-bit register for signal <wr_i_q>.
    Found 8 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  18 D-type flip-flop(s).
	inferred   4 Comparator(s).
	inferred   8 Multiplexer(s).
	inferred   9 Tristate(s).
Unit <can_top> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 211
  1-bit register                   : 160
  8-bit register                   : 37
  2-bit register                   : 1
  3-bit register                   : 5
  4-bit register                   : 3
  9-bit register                   : 2
  6-bit register                   : 1
  7-bit register                   : 1
  15-bit register                  : 1
# Counters                         : 21
  4-bit up counter                 : 2
  6-bit up counter                 : 5
  7-bit updown counter             : 1
  3-bit up counter                 : 10
  5-bit up counter                 : 1
  9-bit up counter                 : 1
  8-bit up counter                 : 1
# Multiplexers                     : 16
  1-bit 16-to-1 multiplexer        : 1
  1-bit 19-to-1 multiplexer        : 2
  2-to-1 multiplexer               : 9
  1-bit 39-to-1 multiplexer        : 1
  1-bit 64-to-1 multiplexer        : 2
  8-bit 8-to-1 multiplexer         : 1
# Tristates                        : 2
  1-bit tristate buffer            : 1
  8-bit tristate buffer            : 1
# Adders/Subtractors               : 25
  6-bit adder                      : 4
  4-bit adder                      : 3
  4-bit subtractor                 : 2
  6-bit subtractor                 : 2
  3-bit adder                      : 3
  9-bit subtractor                 : 4
  10-bit subtractor                : 1
  2-bit adder carry out            : 1
  4-bit adder carry out            : 1
  6-bit adder carry out            : 1
  7-bit addsub                     : 1
  7-bit subtractor                 : 1
  9-bit addsub                     : 1
# Comparators                      : 47
  3-bit comparator less            : 7
  4-bit comparator less            : 4
  6-bit comparator less            : 2
  6-bit comparator equal           : 1
  15-bit comparator not equal      : 1
  9-bit comparator greatequal      : 8
  9-bit comparator lessequal       : 1
  9-bit comparator greater         : 3
  9-bit comparator less            : 2
  8-bit comparator less            : 1
  10-bit comparator less           : 1
  11-bit comparator equal          : 1
  8-bit comparator greater         : 1
  8-bit comparator equal           : 2
  8-bit comparator not equal       : 2
  3-bit comparator equal           : 1
  8-bit comparator greatequal      : 2
  8-bit comparator lessequal       : 2
  6-bit comparator greater         : 2
  9-bit comparator equal           : 2
  4-bit comparator equal           : 1
# Xors                             : 101
  1-bit xor2                       : 101

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <can_top> ...

Optimizing unit <can_crc> ...

Optimizing unit <can_acf> ...

Optimizing unit <can_btl> ...

Optimizing unit <can_fifo> ...

Optimizing unit <can_registers> ...

Optimizing unit <can_bsp> ...
Loading device for application Xst from file '2s300e.nph' in environment C:/Program Files/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Register i_can_bsp_node_bus_off_q equivalent to i_can_registers_node_bus_off_q has been removed
Found area constraint ratio of 100 (+ 5) on block can_top, actual ratio is 30.
FlipFlop i_can_btl_sampled_bit has been replicated 1 time(s)
FlipFlop addr_latched_0 has been replicated 2 time(s)
FlipFlop addr_latched_2 has been replicated 4 time(s)
FlipFlop addr_latched_4 has been replicated 4 time(s)
FlipFlop addr_latched_1 has been replicated 3 time(s)
FlipFlop addr_latched_3 has been replicated 2 time(s)
FlipFlop addr_latched_0 has been replicated 1 time(s)
FlipFlop i_can_registers_MODE_REG0_data_out_0 has been replicated 1 time(s)
FlipFlop i_can_bsp_tx_pointer_21 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s300epq208-6 

 Number of Slices:                     864  out of   3072    28%  
 Number of Slice Flip Flops:           646  out of   6144    10%  
 Number of 4 input LUTs:              1557  out of   6144    25%  
 Number of bonded IOBs:                 17  out of    146    11%  
 Number of BRAMs:                        3  out of      8    37%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_i                              | BUFGP                  | 649   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 29.552ns (Maximum Frequency: 33.839MHz)
   Minimum input arrival time before clock: 20.316ns
   Maximum output required time after clock: 10.090ns
   Maximum combinational path delay: 13.541ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
e:\program\fpga_program\for_fpga\can\ise\canbus/_ngo -i -p xc2s300e-pq208-6
can_top.ngc can_top.ngd 

Reading NGO file "e:/program/fpga_program/for_fpga/can/ise/canbus/can_top.ngc"
...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:477 - clock net 'clk_i_BUFGP' has non-clock connections. These
   problematic connections include:
     pin I2 on block i_can_registers_clkout_SW0 with type LUT4

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Total memory usage is 41736 kilobytes

Writing NGD file "can_top.ngd" ...

Writing NGDBUILD log file "can_top.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Generate Post-Translate Simulation Model".

Completed process "Generate Post-Translate Simulation Model".




Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "can_register_asyn_syn.v"
Module <can_register_asyn_syn> compiled
Compiling source file "can_register_asyn.v"
Module <can_register_asyn> compiled
Compiling source file "can_register.v"
Module <can_register> compiled
Compiling source file "can_registers.v"
Compiling include file "can_defines.v"
Module <can_registers> compiled
No errors in compilation
Analysis of file <can_registers.prj> succeeded.
 
Completed process "Check Syntax".