__projnav.log

基于FPGA的can 总线设计

Analysis of file <can_register_asyn_syn.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <can_register_asyn_syn>.
WARNING:Xst:916 - can_register_asyn_syn.v line 103: Delay is ignored for synthesis.
WARNING:Xst:916 - can_register_asyn_syn.v line 105: Delay is ignored for synthesis.
WARNING:Xst:916 - can_register_asyn_syn.v line 107: Delay is ignored for synthesis.
Module <can_register_asyn_syn> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <can_register_asyn_syn>.
    Related source file is can_register_asyn_syn.v.
    Found 8-bit register for signal <data_out>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <can_register_asyn_syn> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 1
  8-bit register                   : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <can_register_asyn_syn> ...
Loading device for application Xst from file '2s300e.nph' in environment C:/Program Files/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block can_register_asyn_syn, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s300epq208-6 

 Number of Slices:                       5  out of   3072     0%  
 Number of Slice Flip Flops:             8  out of   6144     0%  
 Number of 4 input LUTs:                 9  out of   6144     0%  
 Number of bonded IOBs:                 19  out of    146    13%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 8     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: 6.152ns
   Maximum output required time after clock: 6.514ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "can_register_asyn_syn.v"
Module <can_register_asyn_syn> compiled
Compiling source file "can_register_asyn.v"
Module <can_register_asyn> compiled
Compiling source file "can_register.v"
Module <can_register> compiled
Compiling source file "can_registers.v"
Compiling include file "can_defines.v"
Module <can_registers> compiled
Compiling source file "can_btl.v"
Compiling include file "can_defines.v"
WARNING:HDLCompilers:38 - can_defines.v line 88 Macro 'XILINX_RAM' redefined
Module <can_btl> compiled
Compiling source file "can_crc.v"
Module <can_crc> compiled
Compiling source file "can_acf.v"
Compiling include file "can_defines.v"
WARNING:HDLCompilers:38 - can_defines.v line 88 Macro 'XILINX_RAM' redefined
Module <can_acf> compiled
Compiling source file "can_fifo.v"
Compiling include file "can_defines.v"
WARNING:HDLCompilers:38 - can_defines.v line 88 Macro 'XILINX_RAM' redefined
Module <can_fifo> compiled
Compiling source file "can_ibo.v"
Module <can_ibo> compiled
Compiling source file "can_bsp.v"
Compiling include file "can_defines.v"
WARNING:HDLCompilers:38 - can_defines.v line 88 Macro 'XILINX_RAM' redefined
Module <can_bsp> compiled
Compiling source file "can_top.v"
Compiling include file "can_defines.v"
WARNING:HDLCompilers:38 - can_defines.v line 88 Macro 'XILINX_RAM' redefined
Module <can_top> compiled
No errors in compilation
Analysis of file <can_top.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <can_top>.
WARNING:Xst:916 - can_top.v line 649: Delay is ignored for synthesis.
WARNING:Xst:916 - can_top.v line 651: Delay is ignored for synthesis.
WARNING:Xst:916 - can_top.v line 714: Delay is ignored for synthesis.
WARNING:Xst:916 - can_top.v line 728: Delay is ignored for synthesis.
WARNING:Xst:916 - can_top.v line 729: Delay is ignored for synthesis.
Module <can_top> is correct for synthesis.
 
Analyzing module <can_registers>.
WARNING:Xst:916 - can_registers.v line 443: Delay is ignored for synthesis.
WARNING:Xst:916 - can_registers.v line 444: Delay is ignored for synthesis.
WARNING:Xst:916 - can_registers.v line 445: Delay is ignored for synthesis.
WARNING:Xst:916 - can_registers.v line 446: Delay is ignored for synthesis.
WARNING:Xst:916 - can_registers.v line 447: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
Module <can_registers> is correct for synthesis.
 
Analyzing module <can_register_asyn_syn>.
WARNING:Xst:916 - can_register_asyn_syn.v line 103: Delay is ignored for synthesis.
WARNING:Xst:916 - can_register_asyn_syn.v line 105: Delay is ignored for synthesis.
WARNING:Xst:916 - can_register_asyn_syn.v line 107: Delay is ignored for synthesis.
Module <can_register_asyn_syn> is correct for synthesis.
 
Analyzing module <can_register_asyn>.
WARNING:Xst:916 - can_register_asyn.v line 101: Delay is ignored for synthesis.
WARNING:Xst:916 - can_register_asyn.v line 103: Delay is ignored for synthesis.
Module <can_register_asyn> is correct for synthesis.
 
Analyzing module <can_register_asyn_1>.
WARNING:Xst:916 - can_register_asyn.v line 101: Delay is ignored for synthesis.
WARNING:Xst:916 - can_register_asyn.v line 103: Delay is ignored for synthesis.
Module <can_register_asyn_1> is correct for synthesis.
 
Analyzing module <can_register_asyn_syn_1>.
WARNING:Xst:916 - can_register_asyn_syn.v line 103: Delay is ignored for synthesis.
WARNING:Xst:916 - can_register_asyn_syn.v line 105: Delay is ignored for synthesis.
WARNING:Xst:916 - can_register_asyn_syn.v line 107: Delay is ignored for synthesis.
Module <can_register_asyn_syn_1> is correct for synthesis.
 
Analyzing module <can_register_asyn_syn_2>.
WARNING:Xst:916 - can_register_asyn_syn.v line 103: Delay is ignored for synthesis.
WARNING:Xst:916 - can_register_asyn_syn.v line 105: Delay is ignored for synthesis.
WARNING:Xst:916 - can_register_asyn_syn.v line 107: Delay is ignored for synthesis.
Module <can_register_asyn_syn_2> is correct for synthesis.
 
Analyzing module <can_register>.
WARNING:Xst:916 - can_register.v line 98: Delay is ignored for synthesis.
Module <can_register> is correct for synthesis.
 
Analyzing module <can_register_asyn_2>.
WARNING:Xst:916 - can_register_asyn.v line 101: Delay is ignored for synthesis.
WARNING:Xst:916 - can_register_asyn.v line 103: Delay is ignored for synthesis.
Module <can_register_asyn_2> is correct for synthesis.
 
Analyzing module <can_register_1>.
WARNING:Xst:916 - can_register.v line 98: Delay is ignored for synthesis.
Module <can_register_1> is correct for synthesis.
 
Analyzing module <can_register_2>.
WARNING:Xst:916 - can_register.v line 98: Delay is ignored for synthesis.
Module <can_register_2> is correct for synthesis.
 
Analyzing module <can_btl>.
WARNING:Xst:916 - can_btl.v line 205: Delay is ignored for synthesis.
WARNING:Xst:916 - can_btl.v line 207: Delay is ignored for synthesis.
WARNING:Xst:916 - can_btl.v line 216: Delay is ignored for synthesis.
WARNING:Xst:916 - can_btl.v line 218: Delay is ignored for synthesis.
WARNING:Xst:916 - can_btl.v line 237: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
Module <can_btl> is correct for synthesis.
 
Analyzing module <can_bsp>.
WARNING:Xst:916 - can_bsp.v line 641: Delay is ignored for synthesis.
WARNING:Xst:916 - can_bsp.v line 643: Delay is ignored for synthesis.
WARNING:Xst:916 - can_bsp.v line 653: Delay is ignored for synthesis.
WARNING:Xst:916 - can_bsp.v line 655: Delay is ignored for synthesis.
WARNING:Xst:916 - can_bsp.v line 665: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
can_bsp.v line 1285: Found Parallel Case directive in module <can_bsp>.
can_bsp.v line 1296: Found Parallel Case directive in module <can_bsp>.
can_bsp.v line 1306: Found Parallel Case directive in module <can_bsp>.
INFO:Xst:1433 - Contents of array <tmp_fifo> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <r_calculated_crc> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <extended_chain_std> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <r_calculated_crc> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1433 - Contents of array <basic_chain> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
Module <can_bsp> is correct for synthesis.
 
Analyzing module <can_crc>.
WARNING:Xst:916 - can_crc.v line 96: Delay is ignored for synthesis.
WARNING:Xst:916 - can_crc.v line 100: Delay is ignored for synthesis.
WARNING:Xst:916 - can_crc.v line 102: Delay is ignored for synthesis.
Module <can_crc> is correct for synthesis.
 
Analyzing module <can_acf>.
WARNING:Xst:916 - can_acf.v line 346: Delay is ignored for synthesis.
WARNING:Xst:916 - can_acf.v line 348: Delay is ignored for synthesis.
WARNING:Xst:916 - can_acf.v line 353: Delay is ignored for synthesis.
WARNING:Xst:916 - can_acf.v line 355: Delay is ignored for synthesis.
WARNING:Xst:916 - can_acf.v line 359: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
Module <can_acf> is correct for synthesis.
 
Analyzing module <can_fifo>.
WARNING:Xst:916 - can_fifo.v line 182: Delay is ignored for synthesis.
WARNING:Xst:916 - can_fifo.v line 184: Delay is ignored for synthesis.
WARNING:Xst:916 - can_fifo.v line 194: Delay is ignored for synthesis.
WARNING:Xst:916 - can_fifo.v line 196: Delay is ignored for synthesis.
WARNING:Xst:916 - can_fifo.v line 206: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
Module <can_fifo> is correct for synthesis.
 
Analyzing module <RAMB4_S8_S8>.
Analyzing module <RAMB4_S4_S4>.
Analyzing module <RAMB4_S1_S1>.
Analyzing module <can_ibo>.
Module <can_ibo> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <can_ibo>.
    Related source file is can_ibo.v.
Unit <can_ibo> synthesized.


Synthesizing Unit <can_fifo>.
    Related source file is can_fifo.v.
WARNING:Xst:647 - Input <addr<7:6>> is never used.
WARNING:Xst:647 - Input <fifo_selected> is never used.
    Found 7-bit updown counter for signal <info_cnt>.
    Found 6-bit subtractor for signal <$n0019>.
    Found 7-bit addsub for signal <$n0020>.
    Found 7-bit subtractor for signal <$n0030> created at line 271.
    Found 6-bit adder for signal <$n0032> created at line 231.
    Found 1-bit xor2 for signal <$n0056> created at line 285.
    Found 7-bit register for signal <fifo_cnt>.
    Found 1-bit register for signal <latch_overrun>.
    Found 4-bit up counter for signal <len_cnt>.
    Found 6-bit up counter for signal <rd_info_pointer>.
    Found 6-bit register for signal <rd_pointer>.
    Found 6-bit adder for signal <read_address>.
    Found 6-bit up counter for signal <wr_info_pointer>.
    Found 6-bit up counter for signal <wr_pointer>.
    Found 1-bit register for signal <wr_q>.
    Found 7 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   5 Counter(s).
	inferred  15 D-type flip-flop(s).
	inferred   5 Adder/Subtracter(s).
	inferred   7 Multiplexer(s).
Unit <can_fifo> synthesized.


Synthesizing Unit <can_acf>.
    Related source file is can_acf.v.
    Found 1-bit register for signal <id_ok>.
    Found 1-bit xor2 for signal <$n0102> created at line 293.
    Found 1-bit xor2 for signal <$n0103> created at line 293.
    Found 1-bit xor2 for signal <$n0104> created at line 293.
    Found 1-bit xor2 for signal <$n0105> created at line 293.
    Found 1-bit xor2 for signal <$n0106> created at line 293.
    Found 1-bit xor2 for signal <$n0107> created at line 293.
    Found 1-bit xor2 for signal <$n0108> created at line 293.
    Found 1-bit xor2 for signal <$n0109> created at line 293.
    Found 1-bit xor2 for signal <$n0110> created at line 293.
    Found 1-bit xor2 for signal <$n0111> created at line 293.
    Found 1-bit xor2 for signal <$n0112> created at line 293.
    Found 1-bit xor2 for signal <$n0113> created at line 293.
    Found 1-bit xor2 for signal <$n0114> created at line 293.
    Found 1-bit xor2 for signal <$n0115> created at line 293.
    Found 1-bit xor2 for signal <$n0116> created at line 293.
    Found 1-bit xor2 for signal <$n0117> created at line 293.
    Found 1-bit xor2 for signal <$n0118> created at line 293.
    Found 1-bit xor2 for signal <$n0119> created at line 293.
    Found 1-bit xor2 for signal <$n0120> created at line 293.
    Found 1-bit xor2 for signal <$n0121> created at line 293.
    Found 1-bit xor2 for signal <$n0122> created at line 293.