__projnav.log

基于FPGA的can 总线设计

Project Navigator Auto-Make Log File
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Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "can_register_asyn_syn.v"
Module <can_register_asyn_syn> compiled
Compiling source file "can_register_asyn.v"
Module <can_register_asyn> compiled
Compiling source file "can_register.v"
Module <can_register> compiled
Compiling source file "can_registers.v"
Compiling include file "can_defines.v"
Module <can_registers> compiled
Compiling source file "can_btl.v"
Compiling include file "can_defines.v"
WARNING:HDLCompilers:38 - can_defines.v line 85 Macro 'ACTEL_APA_RAM' redefined
Module <can_btl> compiled
Compiling source file "can_crc.v"
Module <can_crc> compiled
Compiling source file "can_acf.v"
Compiling include file "can_defines.v"
WARNING:HDLCompilers:38 - can_defines.v line 85 Macro 'ACTEL_APA_RAM' redefined
Module <can_acf> compiled
Compiling source file "can_fifo.v"
Compiling include file "can_defines.v"
WARNING:HDLCompilers:38 - can_defines.v line 85 Macro 'ACTEL_APA_RAM' redefined
Module <can_fifo> compiled
Compiling source file "can_ibo.v"
Module <can_ibo> compiled
Compiling source file "can_bsp.v"
Compiling include file "can_defines.v"
WARNING:HDLCompilers:38 - can_defines.v line 85 Macro 'ACTEL_APA_RAM' redefined
Module <can_bsp> compiled
Compiling source file "can_top.v"
Compiling include file "can_defines.v"
WARNING:HDLCompilers:38 - can_defines.v line 85 Macro 'ACTEL_APA_RAM' redefined
Module <can_top> compiled
No errors in compilation
Analysis of file <can_top.prj> succeeded.
 
Completed process "Check Syntax".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "can_register_asyn_syn.v"
Module <can_register_asyn_syn> compiled
Compiling source file "can_register_asyn.v"
Module <can_register_asyn> compiled
Compiling source file "can_register.v"
Module <can_register> compiled
Compiling source file "can_registers.v"
Compiling include file "can_defines.v"
Module <can_registers> compiled
Compiling source file "can_btl.v"
Compiling include file "can_defines.v"
WARNING:HDLCompilers:38 - can_defines.v line 85 Macro 'ACTEL_APA_RAM' redefined
Module <can_btl> compiled
Compiling source file "can_crc.v"
Module <can_crc> compiled
Compiling source file "can_acf.v"
Compiling include file "can_defines.v"
WARNING:HDLCompilers:38 - can_defines.v line 85 Macro 'ACTEL_APA_RAM' redefined
Module <can_acf> compiled
Compiling source file "can_fifo.v"
Compiling include file "can_defines.v"
WARNING:HDLCompilers:38 - can_defines.v line 85 Macro 'ACTEL_APA_RAM' redefined
Module <can_fifo> compiled
Compiling source file "can_ibo.v"
Module <can_ibo> compiled
Compiling source file "can_bsp.v"
Compiling include file "can_defines.v"
WARNING:HDLCompilers:38 - can_defines.v line 85 Macro 'ACTEL_APA_RAM' redefined
Module <can_bsp> compiled
Compiling source file "can_top.v"
Compiling include file "can_defines.v"
WARNING:HDLCompilers:38 - can_defines.v line 85 Macro 'ACTEL_APA_RAM' redefined
Module <can_top> compiled
No errors in compilation
Analysis of file <can_top.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
ERROR:HDLCompilers:87 - can_fifo.v line 314 Could not find module/primitive 'actel_ram_64x8_sync'
ERROR:HDLCompilers:87 - can_fifo.v line 328 Could not find module/primitive 'actel_ram_64x4_sync'
ERROR:HDLCompilers:87 - can_fifo.v line 342 Could not find module/primitive 'actel_ram_64x1_sync'
--> 

Total memory usage is 48688 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "can_fifo.v"
Compiling include file "can_defines.v"
Module <can_fifo> compiled
No errors in compilation
Analysis of file <can_fifo.prj> succeeded.
 
Completed process "Check Syntax".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "can_fifo.v"
Compiling include file "can_defines.v"
Module <can_fifo> compiled
No errors in compilation
Analysis of file <can_fifo.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <can_fifo>.
WARNING:Xst:916 - can_fifo.v line 182: Delay is ignored for synthesis.
WARNING:Xst:916 - can_fifo.v line 184: Delay is ignored for synthesis.
WARNING:Xst:916 - can_fifo.v line 194: Delay is ignored for synthesis.
WARNING:Xst:916 - can_fifo.v line 196: Delay is ignored for synthesis.
WARNING:Xst:916 - can_fifo.v line 206: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
Module <can_fifo> is correct for synthesis.
 
Analyzing module <RAMB4_S8_S8>.
Analyzing module <RAMB4_S4_S4>.
Analyzing module <RAMB4_S1_S1>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <can_fifo>.
    Related source file is can_fifo.v.
WARNING:Xst:647 - Input <addr<7:6>> is never used.
WARNING:Xst:647 - Input <fifo_selected> is never used.
    Found 7-bit updown counter for signal <info_cnt>.
    Found 6-bit subtractor for signal <$n0019>.
    Found 7-bit addsub for signal <$n0020>.
    Found 7-bit subtractor for signal <$n0030> created at line 271.
    Found 6-bit adder for signal <$n0032> created at line 231.
    Found 1-bit xor2 for signal <$n0056> created at line 285.
    Found 7-bit register for signal <fifo_cnt>.
    Found 1-bit register for signal <latch_overrun>.
    Found 4-bit up counter for signal <len_cnt>.
    Found 6-bit up counter for signal <rd_info_pointer>.
    Found 6-bit register for signal <rd_pointer>.
    Found 6-bit adder for signal <read_address>.
    Found 6-bit up counter for signal <wr_info_pointer>.
    Found 6-bit up counter for signal <wr_pointer>.
    Found 1-bit register for signal <wr_q>.
    Found 7 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   5 Counter(s).
	inferred  15 D-type flip-flop(s).
	inferred   5 Adder/Subtracter(s).
	inferred   7 Multiplexer(s).
Unit <can_fifo> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 4
  1-bit register                   : 2
  6-bit register                   : 1
  7-bit register                   : 1
# Counters                         : 5
  4-bit up counter                 : 1
  6-bit up counter                 : 3
  7-bit updown counter             : 1
# Multiplexers                     : 1
  2-to-1 multiplexer               : 1
# Adders/Subtractors               : 5
  6-bit adder                      : 2
  6-bit subtractor                 : 1
  7-bit addsub                     : 1
  7-bit subtractor                 : 1
# Xors                             : 1
  1-bit xor2                       : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <can_fifo> ...
Loading device for application Xst from file '2s300e.nph' in environment C:/Program Files/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block can_fifo, actual ratio is 2.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s300epq208-6 

 Number of Slices:                      64  out of   3072     2%  
 Number of Slice Flip Flops:            44  out of   6144     0%  
 Number of 4 input LUTs:               111  out of   6144     1%  
 Number of bonded IOBs:                 36  out of    146    24%  
 Number of BRAMs:                        3  out of      8    37%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 47    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 13.017ns (Maximum Frequency: 76.823MHz)
   Minimum input arrival time before clock: 10.841ns
   Maximum output required time after clock: 11.718ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
-------------------------------------




Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "can_register_asyn_syn.v"
Module <can_register_asyn_syn> compiled
No errors in compilation
Analysis of file <can_register_asyn_syn.prj> succeeded.
 
Completed process "Check Syntax".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "can_register_asyn_syn.v"
Module <can_register_asyn_syn> compiled
No errors in compilation