canbus.npl

基于FPGA的can 总线设计

JDF G
// Created by Project Navigator ver 1.0
PROJECT canbus
DESIGN canbus
DEVFAM spartan2e
DEVFAMTIME 0
DEVICE xc2s300e
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE can_defines.v
STIMULUS can_testbench_defines.v
STIMULUS timescale.v
STIMULUS can_testbench.v
SOURCE can_top.v
SOURCE can_bsp.v
SOURCE can_btl.v
SOURCE can_registers.v
SOURCE can_acf.v
SOURCE can_crc.v
SOURCE can_fifo.v
SOURCE can_ibo.v
SOURCE can_register_asyn.v
SOURCE can_register.v
SOURCE can_register_asyn_syn.v
[STRATEGY-LIST]
Normal=True