pod552.asm

哎

;      REV.  1.0     JUNE 13, 1988
S0CON  DATA  098H   ;Serial Port 0 Control
S0BUF  DATA  099H   ;Serial Port 0 Buffer
IEN0   DATA  0A8H   ;Interrupt Enable Register 0
CML0   DATA  0A9H   ;Compare 0 - Low Byte
CML1   DATA  0AAH   ;Compare 1 - Low Byte
CML2   DATA  0ABH   ;Compare 2 - Low Byte
CTL0   DATA  0ACH   ;Capture 0 - Low Byte
CTL1   DATA  0ADH   ;Capture 1 - Low Byte
CTL2   DATA  0AEH   ;Capture 2 - Low Byte
CTL3   DATA  0AFH   ;Capture 3 - Low Byte
IP0    DATA  0B8H   ;Interrupt Priority Register 0
P4     DATA  0C0H   ;Port 4
P5     DATA  0C4H   ;Port 5
ADCON  DATA  0C5H   ;A/D Converter Control
ADCH   DATA  0C6H   ;A/D Converter High Byte
TM2IR  DATA  0C8H   ;Timer 2 Interrupt Flags
CMH0   DATA  0C9H   ;Compare 0 - High Byte
CMH1   DATA  0CAH   ;Compare 1 - High Byte
CMH2   DATA  0CBH   ;Compare 2 - High Byte
CTH0   DATA  0CCH   ;Capture 0 - High Byte
CTH1   DATA  0CDH   ;Capture 1 - High Byte
CTH2   DATA  0CEH   ;Capture 2 - High Byte
CTH3   DATA  0CFH   ;Capture 3 - High Byte
S1CON  DATA  0D8H   ;Serial Port 1 Control
S1STA  DATA  0D9H   ;Serial Port 1 Status
S1DAT  DATA  0DAH   ;Serial Port 1 Data
S1ADR  DATA  0DBH   ;Serial Port 1 Slave Address
IEN1   DATA  0E8H   ;Interrupt Enable Register 1
TM2CON DATA  0EAH   ;Timer 2 Counter Control
CTCON  DATA  0EBH   ;Capture Control
TML2   DATA  0ECH   ;Timer 2 - Low Byte
TMH2   DATA  0EDH   ;Timer 2 - High Byte
STE    DATA  0EEH   ;Set Enable
RTE    DATA  0EFH   ;Reset/Toggle Enable
IP1    DATA  0F8H   ;Interrupt Priority Register 1
PWM0   DATA  0FCH   ;Pulse Width Register 0
PWM1   DATA  0FDH   ;Pulse Width Register 1
PWMP   DATA  0FEH   ;Prescaler Frequency Control
T3     DATA  0FFH   ;Watchdog Timer
CT0I   BIT   090H   ;P1.0 - Capture/Timer Input 0
CT1I   BIT   091H   ;P1.1 - Capture/Timer Input 1
CT2I   BIT   092H   ;P1.2 - Capture/Timer Input 2
CT3I   BIT   093H   ;P1.3 - Capture/Timer Input 3
T2     BIT   094H   ;P1.4 - T2 Event Input
RT2    BIT   095H   ;P1.5 - T2 Timer Reset Signal
SCL    BIT   096H   ;P1.6 - Serial Port Clock Line I2C
SDA    BIT   097H   ;P1.7 - Serial Port Data Line I2C
ES0    BIT   0ACH   ;IEN0.4 - Serial Port 0 Interrupt Enable
ES1    BIT   0ADH   ;IEN0.5 - Serial Port 1 Interrupt Enable
EAD    BIT   0AEH   ;IEN0.6 - Enable A/D Interrupt
RXD    BIT   0B0H   ;P3.0 - Serial Port Receive Input
TXD    BIT   0B1H   ;P3.1 - Serial Port Transmit Output
INT0   BIT   0B2H   ;P3.2 - External Interrupt 0 Input
INT1   BIT   0B3H   ;P3.3 - External Interrupt 1 Input
T0     BIT   0B4H   ;P3.4 - Timer 0 Count Input
T1     BIT   0B5H   ;P3.5 - Timer 1 Count Input
WR     BIT   0B6H   ;P3.6 - Write Control For External Memory
RD     BIT   0B7H   ;P3.7 - Read Control For External Memory
PS0    BIT   0BCH   ;IP0.4 - SIO0 Priority
PS1    BIT   0BDH   ;IP0.5 - SIO1 Priority
PAD    BIT   0BEH   ;IP0.6 - A/D Priority
CMSR0  BIT   0C0H   ;P4.0 - T2 Compare and Set/Reset Output
CMSR1  BIT   0C1H   ;P4.1 - T2 Compare and Set/Reset Output
CMSR2  BIT   0C2H   ;P4.2 - T2 Compare and Set/Reset Output
CMSR3  BIT   0C3H   ;P4.3 - T2 Compare and Set/Reset Output
CMSR4  BIT   0C4H   ;P4.4 - T2 Compare and Set/Reset Output
CMSR5  BIT   0C5H   ;P4.5 - T2 Compare and Set/Reset Output
CMT0   BIT   0C6H   ;P4.6 - T2 Compare and Toggle Output
CMT1   BIT   0C7H   ;P4.7 - T2 Compare and Toggle Output
CTI0   BIT   0C8H   ;TM2IR.0 - T2 Capture 0
CTI1   BIT   0C9H   ;TM2IR.1 - T2 Capture 1
CTI2   BIT   0CAH   ;TM2IR.2 - T2 Capture 2
CTI3   BIT   0CBH   ;TM2IR.3 - T2 Capture 3
CMI0   BIT   0CCH   ;TM2IR.4 - T2 Comparator 0
CMI1   BIT   0CDH   ;TM2IR.5 - T2 Comparator 1
CMI2   BIT   0CEH   ;TM2IR.6 - T2 Comparator 2
T2OV   BIT   0CFH   ;TM2IR.7 - T2 Overflow
F1     BIT   0D1H   ;PSW.1 - Flag 1
CR0    BIT   0D8H   ;S1CON.0 - Clock Rate 0;
CR1    BIT   0D9H   ;S1CON.1 - Clock Rate 1
AA     BIT   0DAH   ;S1CON.2 - Assert Acknowledge
SI     BIT   0DBH   ;S1CON.3 - Serial I/O Interrupt
STO    BIT   0DCH   ;S1CON.4 - Stop Flag
STA    BIT   0DDH   ;S1CON.5 - Start Flag
ENS1   BIT   0DEH   ;S1CON.6 - Enable Serial I/O
ECT0   BIT   0E8H   ;IEN1.0 - Enable T2 Capture 0
ECT1   BIT   0E9H   ;IEN1.1 - Enable T2 Capture 1
ECT2   BIT   0EAH   ;IEN1.2 - Enable T2 Capture 2
ECT3   BIT   0EBH   ;IEN1.3 - Enable T2 Capture 3
ECM0   BIT   0ECH   ;IEN1.4 - Enable T2 Comparator 0
ECM1   BIT   0EDH   ;IEN1.5 - Enable T2 Comparator 1
ECM2   BIT   0EEH   ;IEN1.6 - Enable T2 Comparator 2
PCT0   BIT   0F8H   ;IP1.0 - T2 Capture 0
PCT1   BIT   0F9H   ;IP1.1 - T2 Capture 1
PCT2   BIT   0FAH   ;IP1.2 - T2 Capture 2
PCT3   BIT   0FBH   ;IP1.3 - T2 Capture 3
PCM0   BIT   0FCH   ;IP1.4 - T2 Comparator 0
PCM1   BIT   0FDH   ;IP1.5 - T2 Comparator 1
PCM2   BIT   0FEH   ;IP1.6 - T2 Comparator 2