📄 stm8s_tim1.ls
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3661 0468 84 pop a
3662 0469 81 ret
3720 ; 1367 void TIM1_ForcedOC1Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
3720 ; 1368 {
3721 switch .text
3722 046a _TIM1_ForcedOC1Config:
3724 046a 88 push a
3725 00000000 OFST: set 0
3728 ; 1370 assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
3730 ; 1373 TIM1->CCMR1 = (u8)((TIM1->CCMR1 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction);
3732 046b c65258 ld a,21080
3733 046e a48f and a,#143
3734 0470 1a01 or a,(OFST+1,sp)
3735 0472 c75258 ld 21080,a
3736 ; 1374 }
3739 0475 84 pop a
3740 0476 81 ret
3776 ; 1395 void TIM1_ForcedOC2Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
3776 ; 1396 {
3777 switch .text
3778 0477 _TIM1_ForcedOC2Config:
3780 0477 88 push a
3781 00000000 OFST: set 0
3784 ; 1398 assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
3786 ; 1401 TIM1->CCMR2 = (u8)((TIM1->CCMR2 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction);
3788 0478 c65259 ld a,21081
3789 047b a48f and a,#143
3790 047d 1a01 or a,(OFST+1,sp)
3791 047f c75259 ld 21081,a
3792 ; 1402 }
3795 0482 84 pop a
3796 0483 81 ret
3832 ; 1423 void TIM1_ForcedOC3Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
3832 ; 1424 {
3833 switch .text
3834 0484 _TIM1_ForcedOC3Config:
3836 0484 88 push a
3837 00000000 OFST: set 0
3840 ; 1426 assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
3842 ; 1429 TIM1->CCMR3 = (u8)((TIM1->CCMR3 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction);
3844 0485 c6525a ld a,21082
3845 0488 a48f and a,#143
3846 048a 1a01 or a,(OFST+1,sp)
3847 048c c7525a ld 21082,a
3848 ; 1430 }
3851 048f 84 pop a
3852 0490 81 ret
3888 ; 1451 void TIM1_ForcedOC4Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
3888 ; 1452 {
3889 switch .text
3890 0491 _TIM1_ForcedOC4Config:
3892 0491 88 push a
3893 00000000 OFST: set 0
3896 ; 1454 assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
3898 ; 1457 TIM1->CCMR4 = (u8)((TIM1->CCMR4 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction);
3900 0492 c6525b ld a,21083
3901 0495 a48f and a,#143
3902 0497 1a01 or a,(OFST+1,sp)
3903 0499 c7525b ld 21083,a
3904 ; 1458 }
3907 049c 84 pop a
3908 049d 81 ret
3944 ; 1476 void TIM1_ARRPreloadConfig(FunctionalState NewState)
3944 ; 1477 {
3945 switch .text
3946 049e _TIM1_ARRPreloadConfig:
3950 ; 1479 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
3952 ; 1482 if (NewState != DISABLE)
3954 049e 4d tnz a
3955 049f 2706 jreq L7002
3956 ; 1484 TIM1->CR1 |= TIM1_CR1_ARPE;
3958 04a1 721e5250 bset 21072,#7
3960 04a5 2004 jra L1102
3961 04a7 L7002:
3962 ; 1488 TIM1->CR1 &= (u8)(~TIM1_CR1_ARPE);
3964 04a7 721f5250 bres 21072,#7
3965 04ab L1102:
3966 ; 1490 }
3969 04ab 81 ret
4004 ; 1508 void TIM1_SelectCOM(FunctionalState NewState)
4004 ; 1509 {
4005 switch .text
4006 04ac _TIM1_SelectCOM:
4010 ; 1511 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4012 ; 1514 if (NewState != DISABLE)
4014 04ac 4d tnz a
4015 04ad 2706 jreq L1302
4016 ; 1516 TIM1->CR2 |= TIM1_CR2_COMS;
4018 04af 72145251 bset 21073,#2
4020 04b3 2004 jra L3302
4021 04b5 L1302:
4022 ; 1520 TIM1->CR2 &= (u8)(~TIM1_CR2_COMS);
4024 04b5 72155251 bres 21073,#2
4025 04b9 L3302:
4026 ; 1522 }
4029 04b9 81 ret
4065 ; 1539 void TIM1_CCPreloadControl(FunctionalState NewState)
4065 ; 1540 {
4066 switch .text
4067 04ba _TIM1_CCPreloadControl:
4071 ; 1542 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4073 ; 1545 if (NewState != DISABLE)
4075 04ba 4d tnz a
4076 04bb 2706 jreq L3502
4077 ; 1547 TIM1->CR2 |= TIM1_CR2_CCPC;
4079 04bd 72105251 bset 21073,#0
4081 04c1 2004 jra L5502
4082 04c3 L3502:
4083 ; 1551 TIM1->CR2 &= (u8)(~TIM1_CR2_CCPC);
4085 04c3 72115251 bres 21073,#0
4086 04c7 L5502:
4087 ; 1553 }
4090 04c7 81 ret
4126 ; 1571 void TIM1_OC1PreloadConfig(FunctionalState NewState)
4126 ; 1572 {
4127 switch .text
4128 04c8 _TIM1_OC1PreloadConfig:
4132 ; 1574 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4134 ; 1577 if (NewState != DISABLE)
4136 04c8 4d tnz a
4137 04c9 2706 jreq L5702
4138 ; 1579 TIM1->CCMR1 |= TIM1_CCMR_OCxPE;
4140 04cb 72165258 bset 21080,#3
4142 04cf 2004 jra L7702
4143 04d1 L5702:
4144 ; 1583 TIM1->CCMR1 &= (u8)(~TIM1_CCMR_OCxPE);
4146 04d1 72175258 bres 21080,#3
4147 04d5 L7702:
4148 ; 1585 }
4151 04d5 81 ret
4187 ; 1603 void TIM1_OC2PreloadConfig(FunctionalState NewState)
4187 ; 1604 {
4188 switch .text
4189 04d6 _TIM1_OC2PreloadConfig:
4193 ; 1606 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4195 ; 1609 if (NewState != DISABLE)
4197 04d6 4d tnz a
4198 04d7 2706 jreq L7112
4199 ; 1611 TIM1->CCMR2 |= TIM1_CCMR_OCxPE;
4201 04d9 72165259 bset 21081,#3
4203 04dd 2004 jra L1212
4204 04df L7112:
4205 ; 1615 TIM1->CCMR2 &= (u8)(~TIM1_CCMR_OCxPE);
4207 04df 72175259 bres 21081,#3
4208 04e3 L1212:
4209 ; 1617 }
4212 04e3 81 ret
4248 ; 1635 void TIM1_OC3PreloadConfig(FunctionalState NewState)
4248 ; 1636 {
4249 switch .text
4250 04e4 _TIM1_OC3PreloadConfig:
4254 ; 1638 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4256 ; 1641 if (NewState != DISABLE)
4258 04e4 4d tnz a
4259 04e5 2706 jreq L1412
4260 ; 1643 TIM1->CCMR3 |= TIM1_CCMR_OCxPE;
4262 04e7 7216525a bset 21082,#3
4264 04eb 2004 jra L3412
4265 04ed L1412:
4266 ; 1647 TIM1->CCMR3 &= (u8)(~TIM1_CCMR_OCxPE);
4268 04ed 7217525a bres 21082,#3
4269 04f1 L3412:
4270 ; 1649 }
4273 04f1 81 ret
4309 ; 1668 void TIM1_OC4PreloadConfig(FunctionalState NewState)
4309 ; 1669 {
4310 switch .text
4311 04f2 _TIM1_OC4PreloadConfig:
4315 ; 1671 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4317 ; 1674 if (NewState != DISABLE)
4319 04f2 4d tnz a
4320 04f3 2706 jreq L3612
4321 ; 1676 TIM1->CCMR4 |= TIM1_CCMR_OCxPE;
4323 04f5 7216525b bset 21083,#3
4325 04f9 2004 jra L5612
4326 04fb L3612:
4327 ; 1680 TIM1->CCMR4 &= (u8)(~TIM1_CCMR_OCxPE);
4329 04fb 7217525b bres 21083,#3
4330 04ff L5612:
4331 ; 1682 }
4334 04ff 81 ret
4369 ; 1699 void TIM1_OC1FastConfig(FunctionalState NewState)
4369 ; 1700 {
4370 switch .text
4371 0500 _TIM1_OC1FastConfig:
4375 ; 1702 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4377 ; 1705 if (NewState != DISABLE)
4379 0500 4d tnz a
4380 0501 2706 jreq L5022
4381 ; 1707 TIM1->CCMR1 |= TIM1_CCMR_OCxFE;
4383 0503 72145258 bset 21080,#2
4385 0507 2004 jra L7022
4386 0509 L5022:
4387 ; 1711 TIM1->CCMR1 &= (u8)(~TIM1_CCMR_OCxFE);
4389 0509 72155258 bres 21080,#2
4390 050d L7022:
4391 ; 1713 }
4394 050d 81 ret
4429 ; 1732 void TIM1_OC2FastConfig(FunctionalState NewState)
4429 ; 1733 {
4430 switch .text
4431 050e _TIM1_OC2FastConfig:
4435 ; 1735 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4437 ; 1738 if (NewState != DISABLE)
4439 050e 4d tnz a
4440 050f 2706 jreq L7222
4441 ; 1740 TIM1->CCMR2 |= TIM1_CCMR_OCxFE;
4443 0511 72145259 bset 21081,#2
4445 0515 2004 jra L1322
4446 0517 L7222:
4447 ; 1744 TIM1->CCMR2 &= (u8)(~TIM1_CCMR_OCxFE);
4449 0517 72155259 bres 21081,#2
4450 051b L1322:
4451 ; 1746 }
4454 051b 81 ret
4489 ; 1764 void TIM1_OC3FastConfig(FunctionalState NewState)
4489 ; 1765 {
4490 switch .text
4491 051c _TIM1_OC3FastConfig:
4495 ; 1767 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4497 ; 1770 if (NewState != DISABLE)
4499 051c 4d tnz a
4500 051d 2706 jreq L1522
4501 ; 1772 TIM1->CCMR3 |= TIM1_CCMR_OCxFE;
4503 051f 7214525a bset 21082,#2
4505 0523 2004 jra L3522
4506 0525 L1522:
4507 ; 1776 TIM1->CCMR3 &= (u8)(~TIM1_CCMR_OCxFE);
4509 0525 7215525a bres 21082,#2
4510 0529 L3522:
4511 ; 1778 }
4514 0529 81 ret
4549 ; 1796 void TIM1_OC4FastConfig(FunctionalState NewState)
4549 ; 1797 {
4550 switch .text
4551 052a _TIM1_OC4FastConfig:
4555 ; 1799 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4557 ; 1802 if (NewState != DISABLE)
4559 052a 4d tnz a
4560 052b 2706 jreq L3722
4561 ; 1804 TIM1->CCMR4 |= TIM1_CCMR_OCxFE;
4563 052d 7214525b bset 21083,#2
4565 0531 2004 jra L5722
4566 0533 L3722:
4567 ; 1808 TIM1->CCMR4 &= (u8)(~TIM1_CCMR_OCxFE);
4569 0533 7215525b bres 21083,#2
4570 0537 L5722:
4571 ; 1810 }
4574 0537 81 ret
4679 ; 1836 void TIM1_GenerateEvent(TIM1_EventSource_TypeDef TIM1_E⌨️ 快捷键说明
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