📄 stm8s_tim1.ls
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2660 0373 89 pushw x
2661 00000000 OFST: set 0
2664 ; 939 assert_param(IS_TIM1_TIXCLK_SOURCE_OK(TIM1_TIxExternalCLKSource));
2666 ; 940 assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity));
2668 ; 941 assert_param(IS_TIM1_IC_FILTER_OK(ICFilter));
2670 ; 944 if (TIM1_TIxExternalCLKSource == TIM1_TIXEXTERNALCLK1SOURCE_TI2)
2672 0374 9e ld a,xh
2673 0375 a160 cp a,#96
2674 0377 260f jrne L1521
2675 ; 946 TI2_Config(TIM1_ICPolarity, TIM1_ICSELECTION_DIRECTTI, ICFilter);
2677 0379 7b05 ld a,(OFST+5,sp)
2678 037b 88 push a
2679 037c ae0001 ldw x,#1
2680 037f 7b03 ld a,(OFST+3,sp)
2681 0381 95 ld xh,a
2682 0382 cd083c call L5_TI2_Config
2684 0385 84 pop a
2686 0386 200d jra L3521
2687 0388 L1521:
2688 ; 950 TI1_Config(TIM1_ICPolarity, TIM1_ICSELECTION_DIRECTTI, ICFilter);
2690 0388 7b05 ld a,(OFST+5,sp)
2691 038a 88 push a
2692 038b ae0001 ldw x,#1
2693 038e 7b03 ld a,(OFST+3,sp)
2694 0390 95 ld xh,a
2695 0391 cd080c call L3_TI1_Config
2697 0394 84 pop a
2698 0395 L3521:
2699 ; 954 TIM1_SelectInputTrigger(TIM1_TIxExternalCLKSource);
2701 0395 7b01 ld a,(OFST+1,sp)
2702 0397 ad0a call _TIM1_SelectInputTrigger
2704 ; 957 TIM1->SMCR |= (u8)(TIM1_SLAVEMODE_EXTERNAL1);
2706 0399 c65252 ld a,21074
2707 039c aa07 or a,#7
2708 039e c75252 ld 21074,a
2709 ; 958 }
2712 03a1 85 popw x
2713 03a2 81 ret
2784 ; 979 void TIM1_SelectInputTrigger(TIM1_TS_TypeDef TIM1_InputTriggerSource)
2784 ; 980 {
2785 switch .text
2786 03a3 _TIM1_SelectInputTrigger:
2788 03a3 88 push a
2789 00000000 OFST: set 0
2792 ; 982 assert_param(IS_TIM1_TRIGGER_SELECTION_OK(TIM1_InputTriggerSource));
2794 ; 985 TIM1->SMCR = (u8)((TIM1->SMCR & (u8)(~TIM1_SMCR_TS)) | (u8)TIM1_InputTriggerSource);
2796 03a4 c65252 ld a,21074
2797 03a7 a48f and a,#143
2798 03a9 1a01 or a,(OFST+1,sp)
2799 03ab c75252 ld 21074,a
2800 ; 986 }
2803 03ae 84 pop a
2804 03af 81 ret
2840 ; 1005 void TIM1_UpdateDisableConfig(FunctionalState NewState)
2840 ; 1006 {
2841 switch .text
2842 03b0 _TIM1_UpdateDisableConfig:
2846 ; 1008 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2848 ; 1011 if (NewState != DISABLE)
2850 03b0 4d tnz a
2851 03b1 2706 jreq L5231
2852 ; 1013 TIM1->CR1 |= TIM1_CR1_UDIS;
2854 03b3 72125250 bset 21072,#1
2856 03b7 2004 jra L7231
2857 03b9 L5231:
2858 ; 1017 TIM1->CR1 &= (u8)(~TIM1_CR1_UDIS);
2860 03b9 72135250 bres 21072,#1
2861 03bd L7231:
2862 ; 1019 }
2865 03bd 81 ret
2923 ; 1038 void TIM1_UpdateRequestConfig(TIM1_UpdateSource_TypeDef TIM1_UpdateSource)
2923 ; 1039 {
2924 switch .text
2925 03be _TIM1_UpdateRequestConfig:
2929 ; 1041 assert_param(IS_TIM1_UPDATE_SOURCE_OK(TIM1_UpdateSource));
2931 ; 1044 if (TIM1_UpdateSource != TIM1_UPDATESOURCE_GLOBAL)
2933 03be 4d tnz a
2934 03bf 2706 jreq L7531
2935 ; 1046 TIM1->CR1 |= TIM1_CR1_URS;
2937 03c1 72145250 bset 21072,#2
2939 03c5 2004 jra L1631
2940 03c7 L7531:
2941 ; 1050 TIM1->CR1 &= (u8)(~TIM1_CR1_URS);
2943 03c7 72155250 bres 21072,#2
2944 03cb L1631:
2945 ; 1052 }
2948 03cb 81 ret
2984 ; 1070 void TIM1_SelectHallSensor(FunctionalState NewState)
2984 ; 1071 {
2985 switch .text
2986 03cc _TIM1_SelectHallSensor:
2990 ; 1073 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2992 ; 1076 if (NewState != DISABLE)
2994 03cc 4d tnz a
2995 03cd 2706 jreq L1041
2996 ; 1078 TIM1->CR2 |= TIM1_CR2_TI1S;
2998 03cf 721e5251 bset 21073,#7
3000 03d3 2004 jra L3041
3001 03d5 L1041:
3002 ; 1082 TIM1->CR2 &= (u8)(~TIM1_CR2_TI1S);
3004 03d5 721f5251 bres 21073,#7
3005 03d9 L3041:
3006 ; 1084 }
3009 03d9 81 ret
3066 ; 1104 void TIM1_SelectOnePulseMode(TIM1_OPMode_TypeDef TIM1_OPMode)
3066 ; 1105 {
3067 switch .text
3068 03da _TIM1_SelectOnePulseMode:
3072 ; 1107 assert_param(IS_TIM1_OPM_MODE_OK(TIM1_OPMode));
3074 ; 1110 if (TIM1_OPMode != TIM1_OPMODE_REPETITIVE)
3076 03da 4d tnz a
3077 03db 2706 jreq L3341
3078 ; 1112 TIM1->CR1 |= TIM1_CR1_OPM;
3080 03dd 72165250 bset 21072,#3
3082 03e1 2004 jra L5341
3083 03e3 L3341:
3084 ; 1116 TIM1->CR1 &= (u8)(~TIM1_CR1_OPM);
3086 03e3 72175250 bres 21072,#3
3087 03e7 L5341:
3088 ; 1119 }
3091 03e7 81 ret
3189 ; 1144 void TIM1_SelectOutputTrigger(TIM1_TRGOSource_TypeDef TIM1_TRGOSource)
3189 ; 1145 {
3190 switch .text
3191 03e8 _TIM1_SelectOutputTrigger:
3193 03e8 88 push a
3194 00000000 OFST: set 0
3197 ; 1148 assert_param(IS_TIM1_TRGO_SOURCE_OK(TIM1_TRGOSource));
3199 ; 1150 TIM1->CR2 = (u8)((TIM1->CR2 & (u8)(~TIM1_CR2_MMS )) | (u8) TIM1_TRGOSource);
3201 03e9 c65251 ld a,21073
3202 03ec a48f and a,#143
3203 03ee 1a01 or a,(OFST+1,sp)
3204 03f0 c75251 ld 21073,a
3205 ; 1151 }
3208 03f3 84 pop a
3209 03f4 81 ret
3283 ; 1172 void TIM1_SelectSlaveMode(TIM1_SlaveMode_TypeDef TIM1_SlaveMode)
3283 ; 1173 {
3284 switch .text
3285 03f5 _TIM1_SelectSlaveMode:
3287 03f5 88 push a
3288 00000000 OFST: set 0
3291 ; 1176 assert_param(IS_TIM1_SLAVE_MODE_OK(TIM1_SlaveMode));
3293 ; 1179 TIM1->SMCR = (u8)((TIM1->SMCR & (u8)(~TIM1_SMCR_SMS)) | (u8)TIM1_SlaveMode);
3295 03f6 c65252 ld a,21074
3296 03f9 a4f8 and a,#248
3297 03fb 1a01 or a,(OFST+1,sp)
3298 03fd c75252 ld 21074,a
3299 ; 1181 }
3302 0400 84 pop a
3303 0401 81 ret
3339 ; 1198 void TIM1_SelectMasterSlaveMode(FunctionalState NewState)
3339 ; 1199 {
3340 switch .text
3341 0402 _TIM1_SelectMasterSlaveMode:
3345 ; 1201 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
3347 ; 1204 if (NewState != DISABLE)
3349 0402 4d tnz a
3350 0403 2706 jreq L7451
3351 ; 1206 TIM1->SMCR |= TIM1_SMCR_MSM;
3353 0405 721e5252 bset 21074,#7
3355 0409 2004 jra L1551
3356 040b L7451:
3357 ; 1210 TIM1->SMCR &= (u8)(~TIM1_SMCR_MSM);
3359 040b 721f5252 bres 21074,#7
3360 040f L1551:
3361 ; 1212 }
3364 040f 81 ret
3450 ; 1243 void TIM1_EncoderInterfaceConfig(TIM1_EncoderMode_TypeDef TIM1_EncoderMode,
3450 ; 1244 TIM1_ICPolarity_TypeDef TIM1_IC1Polarity,
3450 ; 1245 TIM1_ICPolarity_TypeDef TIM1_IC2Polarity)
3450 ; 1246 {
3451 switch .text
3452 0410 _TIM1_EncoderInterfaceConfig:
3454 0410 89 pushw x
3455 00000000 OFST: set 0
3458 ; 1250 assert_param(IS_TIM1_ENCODER_MODE_OK(TIM1_EncoderMode));
3460 ; 1251 assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_IC1Polarity));
3462 ; 1252 assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_IC2Polarity));
3464 ; 1255 if (TIM1_IC1Polarity != TIM1_ICPOLARITY_RISING)
3466 0411 9f ld a,xl
3467 0412 4d tnz a
3468 0413 2706 jreq L3161
3469 ; 1257 TIM1->CCER1 |= TIM1_CCER1_CC1P;
3471 0415 7212525c bset 21084,#1
3473 0419 2004 jra L5161
3474 041b L3161:
3475 ; 1261 TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC1P);
3477 041b 7213525c bres 21084,#1
3478 041f L5161:
3479 ; 1264 if (TIM1_IC2Polarity != TIM1_ICPOLARITY_RISING)
3481 041f 0d05 tnz (OFST+5,sp)
3482 0421 2706 jreq L7161
3483 ; 1266 TIM1->CCER1 |= TIM1_CCER1_CC2P;
3485 0423 721a525c bset 21084,#5
3487 0427 2004 jra L1261
3488 0429 L7161:
3489 ; 1270 TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC2P);
3491 0429 721b525c bres 21084,#5
3492 042d L1261:
3493 ; 1273 TIM1->SMCR = (u8)((TIM1->SMCR & (u8)(TIM1_SMCR_MSM | TIM1_SMCR_TS)) | (u8) TIM1_EncoderMode);
3495 042d c65252 ld a,21074
3496 0430 a4f0 and a,#240
3497 0432 1a01 or a,(OFST+1,sp)
3498 0434 c75252 ld 21074,a
3499 ; 1276 TIM1->CCMR1 = (u8)((TIM1->CCMR1 & (u8)(~TIM1_CCMR_CCxS)) | (u8) CCMR_TIxDirect_Set);
3501 0437 c65258 ld a,21080
3502 043a a4fc and a,#252
3503 043c aa01 or a,#1
3504 043e c75258 ld 21080,a
3505 ; 1277 TIM1->CCMR2 = (u8)((TIM1->CCMR2 & (u8)(~TIM1_CCMR_CCxS)) | (u8) CCMR_TIxDirect_Set);
3507 0441 c65259 ld a,21081
3508 0444 a4fc and a,#252
3509 0446 aa01 or a,#1
3510 0448 c75259 ld 21081,a
3511 ; 1279 }
3514 044b 85 popw x
3515 044c 81 ret
3580 ; 1303 void TIM1_PrescalerConfig(u16 Prescaler,
3580 ; 1304 TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode)
3580 ; 1305 {
3581 switch .text
3582 044d _TIM1_PrescalerConfig:
3584 044d 89 pushw x
3585 00000000 OFST: set 0
3588 ; 1307 assert_param(IS_TIM1_PRESCALER_RELOAD_OK(TIM1_PSCReloadMode));
3590 ; 1310 TIM1->PSCRH = (u8)(Prescaler >> 8);
3592 044e 9e ld a,xh
3593 044f c75260 ld 21088,a
3594 ; 1311 TIM1->PSCRL = (u8)(Prescaler);
3596 0452 9f ld a,xl
3597 0453 c75261 ld 21089,a
3598 ; 1314 TIM1->EGR = TIM1_PSCReloadMode;
3600 0456 7b05 ld a,(OFST+5,sp)
3601 0458 c75257 ld 21079,a
3602 ; 1316 }
3605 045b 85 popw x
3606 045c 81 ret
3642 ; 1338 void TIM1_CounterModeConfig(TIM1_CounterMode_TypeDef TIM1_CounterMode)
3642 ; 1339 {
3643 switch .text
3644 045d _TIM1_CounterModeConfig:
3646 045d 88 push a
3647 00000000 OFST: set 0
3650 ; 1341 assert_param(IS_TIM1_COUNTER_MODE_OK(TIM1_CounterMode));
3652 ; 1345 TIM1->CR1 = (u8)((TIM1->CR1 & (u8)((u8)(~TIM1_CR1_CMS) & (u8)(~TIM1_CR1_DIR))) | (u8)TIM1_CounterMode);
3654 045e c65250 ld a,21072
3655 0461 a48f and a,#143
3656 0463 1a01 or a,(OFST+1,sp)
3657 0465 c75250 ld 21072,a
3658 ; 1346 }
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