📄 stm8s_tim1.ls
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847 016f 7b0a ld a,(OFST+7,sp)
848 0171 c75268 ld 21096,a
849 ; 292 }
852 0174 5b05 addw sp,#5
853 0176 81 ret
955 ; 323 void TIM1_OC3Init(TIM1_OCMode_TypeDef TIM1_OCMode,
955 ; 324 TIM1_OutputState_TypeDef TIM1_OutputState,
955 ; 325 TIM1_OutputNState_TypeDef TIM1_OutputNState,
955 ; 326 u16 TIM1_Pulse,
955 ; 327 TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
955 ; 328 TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
955 ; 329 TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
955 ; 330 TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
955 ; 331 {
956 switch .text
957 0177 _TIM1_OC3Init:
959 0177 89 pushw x
960 0178 5203 subw sp,#3
961 00000003 OFST: set 3
964 ; 334 assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
966 ; 335 assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
968 ; 336 assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));
970 ; 337 assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
972 ; 338 assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
974 ; 339 assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
976 ; 340 assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));
978 ; 343 TIM1->CCER2 &= (u8)(~( TIM1_CCER2_CC3E | TIM1_CCER2_CC3NE | TIM1_CCER2_CC3P | TIM1_CCER2_CC3NP));
980 017a c6525d ld a,21085
981 017d a4f0 and a,#240
982 017f c7525d ld 21085,a
983 ; 345 TIM1->CCER2 |= (u8)((TIM1_OutputState & TIM1_CCER2_CC3E ) | (TIM1_OutputNState & TIM1_CCER2_CC3NE ) | (TIM1_OCPolarity & TIM1_CCER2_CC3P ) | (TIM1_OCNPolarity & TIM1_CCER2_CC3NP ));
985 0182 7b0c ld a,(OFST+9,sp)
986 0184 a408 and a,#8
987 0186 6b03 ld (OFST+0,sp),a
988 0188 7b0b ld a,(OFST+8,sp)
989 018a a402 and a,#2
990 018c 6b02 ld (OFST-1,sp),a
991 018e 7b08 ld a,(OFST+5,sp)
992 0190 a404 and a,#4
993 0192 6b01 ld (OFST-2,sp),a
994 0194 9f ld a,xl
995 0195 a401 and a,#1
996 0197 1a01 or a,(OFST-2,sp)
997 0199 1a02 or a,(OFST-1,sp)
998 019b 1a03 or a,(OFST+0,sp)
999 019d ca525d or a,21085
1000 01a0 c7525d ld 21085,a
1001 ; 350 TIM1->CCMR3 = (u8)((TIM1->CCMR3 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_OCMode);
1003 01a3 c6525a ld a,21082
1004 01a6 a48f and a,#143
1005 01a8 1a04 or a,(OFST+1,sp)
1006 01aa c7525a ld 21082,a
1007 ; 353 TIM1->OISR &= (u8)(~(TIM1_OISR_OIS3 | TIM1_OISR_OIS3N));
1009 01ad c6526f ld a,21103
1010 01b0 a4cf and a,#207
1011 01b2 c7526f ld 21103,a
1012 ; 355 TIM1->OISR |= (u8)((TIM1_OISR_OIS3 & TIM1_OCIdleState) | (TIM1_OISR_OIS3N & TIM1_OCNIdleState));
1014 01b5 7b0e ld a,(OFST+11,sp)
1015 01b7 a420 and a,#32
1016 01b9 6b03 ld (OFST+0,sp),a
1017 01bb 7b0d ld a,(OFST+10,sp)
1018 01bd a410 and a,#16
1019 01bf 1a03 or a,(OFST+0,sp)
1020 01c1 ca526f or a,21103
1021 01c4 c7526f ld 21103,a
1022 ; 358 TIM1->CCR3H = (u8)(TIM1_Pulse >> 8);
1024 01c7 7b09 ld a,(OFST+6,sp)
1025 01c9 c75269 ld 21097,a
1026 ; 359 TIM1->CCR3L = (u8)(TIM1_Pulse);
1028 01cc 7b0a ld a,(OFST+7,sp)
1029 01ce c7526a ld 21098,a
1030 ; 361 }
1033 01d1 5b05 addw sp,#5
1034 01d3 81 ret
1106 ; 386 void TIM1_OC4Init(TIM1_OCMode_TypeDef TIM1_OCMode,
1106 ; 387 TIM1_OutputState_TypeDef TIM1_OutputState,
1106 ; 388 u16 TIM1_Pulse,
1106 ; 389 TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
1106 ; 390 TIM1_OCIdleState_TypeDef TIM1_OCIdleState)
1106 ; 391 {
1107 switch .text
1108 01d4 _TIM1_OC4Init:
1110 01d4 89 pushw x
1111 01d5 88 push a
1112 00000001 OFST: set 1
1115 ; 394 assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
1117 ; 395 assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
1119 ; 396 assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
1121 ; 397 assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
1123 ; 402 TIM1->CCER2 &= (u8)(~(TIM1_CCER2_CC4E | TIM1_CCER2_CC4P));
1125 01d6 c6525d ld a,21085
1126 01d9 a4cf and a,#207
1127 01db c7525d ld 21085,a
1128 ; 404 TIM1->CCER2 |= (u8)((TIM1_OutputState & TIM1_CCER2_CC4E ) | (TIM1_OCPolarity & TIM1_CCER2_CC4P ));
1130 01de 7b08 ld a,(OFST+7,sp)
1131 01e0 a420 and a,#32
1132 01e2 6b01 ld (OFST+0,sp),a
1133 01e4 9f ld a,xl
1134 01e5 a410 and a,#16
1135 01e7 1a01 or a,(OFST+0,sp)
1136 01e9 ca525d or a,21085
1137 01ec c7525d ld 21085,a
1138 ; 407 TIM1->CCMR4 = (u8)((TIM1->CCMR4 & (u8)(~TIM1_CCMR_OCM)) | (TIM1_OCMode));
1140 01ef c6525b ld a,21083
1141 01f2 a48f and a,#143
1142 01f4 1a02 or a,(OFST+1,sp)
1143 01f6 c7525b ld 21083,a
1144 ; 410 if (TIM1_OCIdleState != TIM1_OCIDLESTATE_RESET)
1146 01f9 0d09 tnz (OFST+8,sp)
1147 01fb 270a jreq L714
1148 ; 412 TIM1->OISR |= (u8)(~TIM1_CCER2_CC4P);
1150 01fd c6526f ld a,21103
1151 0200 aadf or a,#223
1152 0202 c7526f ld 21103,a
1154 0205 2004 jra L124
1155 0207 L714:
1156 ; 416 TIM1->OISR &= (u8)(~TIM1_OISR_OIS4);
1158 0207 721d526f bres 21103,#6
1159 020b L124:
1160 ; 420 TIM1->CCR4H = (u8)(TIM1_Pulse >> 8);
1162 020b 7b06 ld a,(OFST+5,sp)
1163 020d c7526b ld 21099,a
1164 ; 421 TIM1->CCR4L = (u8)(TIM1_Pulse);
1166 0210 7b07 ld a,(OFST+6,sp)
1167 0212 c7526c ld 21100,a
1168 ; 423 }
1171 0215 5b03 addw sp,#3
1172 0217 81 ret
1375 ; 451 void TIM1_BDTRConfig(TIM1_OSSIState_TypeDef TIM1_OSSIState,
1375 ; 452 TIM1_LockLevel_TypeDef TIM1_LockLevel,
1375 ; 453 u8 TIM1_DeadTime,
1375 ; 454 TIM1_BreakState_TypeDef TIM1_Break,
1375 ; 455 TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity,
1375 ; 456 TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput)
1375 ; 457 {
1376 switch .text
1377 0218 _TIM1_BDTRConfig:
1379 0218 89 pushw x
1380 00000000 OFST: set 0
1383 ; 461 assert_param(IS_TIM1_OSSI_STATE_OK(TIM1_OSSIState));
1385 ; 462 assert_param(IS_TIM1_LOCK_LEVEL_OK(TIM1_LockLevel));
1387 ; 463 assert_param(IS_TIM1_BREAK_STATE_OK(TIM1_Break));
1389 ; 464 assert_param(IS_TIM1_BREAK_POLARITY_OK(TIM1_BreakPolarity));
1391 ; 465 assert_param(IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK(TIM1_AutomaticOutput));
1393 ; 468 TIM1->DTR = (u8)(TIM1_DeadTime);
1395 0219 7b05 ld a,(OFST+5,sp)
1396 021b c7526e ld 21102,a
1397 ; 472 TIM1->BKR = (u8)((u8)TIM1_OSSIState | \
1397 ; 473 (u8)TIM1_LockLevel | \
1397 ; 474 (u8)TIM1_Break | \
1397 ; 475 (u8)TIM1_BreakPolarity | \
1397 ; 476 (u8)TIM1_AutomaticOutput);
1399 021e 9f ld a,xl
1400 021f 1a01 or a,(OFST+1,sp)
1401 0221 1a06 or a,(OFST+6,sp)
1402 0223 1a07 or a,(OFST+7,sp)
1403 0225 1a08 or a,(OFST+8,sp)
1404 0227 c7526d ld 21101,a
1405 ; 478 }
1408 022a 85 popw x
1409 022b 81 ret
1609 ; 511 void TIM1_ICInit(TIM1_Channel_TypeDef TIM1_Channel,
1609 ; 512 TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
1609 ; 513 TIM1_ICSelection_TypeDef TIM1_ICSelection,
1609 ; 514 TIM1_ICPSC_TypeDef TIM1_ICPrescaler,
1609 ; 515 u8 TIM1_ICFilter)
1609 ; 516 {
1610 switch .text
1611 022c _TIM1_ICInit:
1613 022c 89 pushw x
1614 00000000 OFST: set 0
1617 ; 519 assert_param(IS_TIM1_CHANNEL_OK(TIM1_Channel));
1619 ; 520 assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity));
1621 ; 521 assert_param(IS_TIM1_IC_SELECTION_OK(TIM1_ICSelection));
1623 ; 522 assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_ICPrescaler));
1625 ; 523 assert_param(IS_TIM1_IC_FILTER_OK(TIM1_ICFilter));
1627 ; 525 if (TIM1_Channel == TIM1_CHANNEL_1)
1629 022d 9e ld a,xh
1630 022e 4d tnz a
1631 022f 2614 jrne L546
1632 ; 528 TI1_Config(TIM1_ICPolarity,
1632 ; 529 TIM1_ICSelection,
1632 ; 530 TIM1_ICFilter);
1634 0231 7b07 ld a,(OFST+7,sp)
1635 0233 88 push a
1636 0234 7b06 ld a,(OFST+6,sp)
1637 0236 97 ld xl,a
1638 0237 7b03 ld a,(OFST+3,sp)
1639 0239 95 ld xh,a
1640 023a cd080c call L3_TI1_Config
1642 023d 84 pop a
1643 ; 532 TIM1_SetIC1Prescaler(TIM1_ICPrescaler);
1645 023e 7b06 ld a,(OFST+6,sp)
1646 0240 cd06b1 call _TIM1_SetIC1Prescaler
1649 0243 2046 jra L746
1650 0245 L546:
1651 ; 534 else if (TIM1_Channel == TIM1_CHANNEL_2)
1653 0245 7b01 ld a,(OFST+1,sp)
1654 0247 a101 cp a,#1
1655 0249 2614 jrne L156
1656 ; 537 TI2_Config(TIM1_ICPolarity,
1656 ; 538 TIM1_ICSelection,
1656 ; 539 TIM1_ICFilter);
1658 024b 7b07 ld a,(OFST+7,sp)
1659 024d 88 push a
1660 024e 7b06 ld a,(OFST+6,sp)
1661 0250 97 ld xl,a
1662 0251 7b03 ld a,(OFST+3,sp)
1663 0253 95 ld xh,a
1664 0254 cd083c call L5_TI2_Config
1666 0257 84 pop a
1667 ; 541 TIM1_SetIC2Prescaler(TIM1_ICPrescaler);
1669 0258 7b06 ld a,(OFST+6,sp)
1670 025a cd06be call _TIM1_SetIC2Prescaler
1673 025d 202c jra L746
1674 025f L156:
1675 ; 543 else if (TIM1_Channel == TIM1_CHANNEL_3)
1677 025f 7b01 ld a,(OFST+1,sp)
1678 0261 a102 cp a,#2
1679 0263 2614 jrne L556
1680 ; 546 TI3_Config(TIM1_ICPolarity,
1680 ; 547 TIM1_ICSelection,
1680 ; 548 TIM1_ICFilter);
1682 0265 7b07 ld a,(OFST+7,sp)
1683 0267 88 push a
1684 0268 7b06 ld a,(OFST+6,sp)
1685 026a 97 ld xl,a
1686 026b 7b03 ld a,(OFST+3,sp)
1687 026d 95 ld xh,a
1688 026e cd086c call L7_TI3_Config
1690 0271 84 pop a
1691 ; 550 TIM1_SetIC3Prescaler(TIM1_ICPrescaler);
1693 0272 7b06 ld a,(OFST+6,sp)
1694 0274 cd06cb call _TIM1_SetIC3Prescaler
1697 0277 2012 jra L746
1698 0279 L556:
1699 ; 555 TI4_Config(TIM1_ICPolarity,
1699 ; 556 TIM1_ICSelection,
1699 ; 557 TIM1_ICFilter);
1701 0279 7b07 ld a,(OFST+7,sp)
1702 027b 88 push a
1703 027c 7b06 ld a,(OFST+6,sp)
1704 027e 97 ld xl,a
1705 027f 7b03 ld a,(OFST+3,sp)
1706 0281 95 ld xh,a
1707 0282 cd089c call L11_TI4_Config
1709 0285 84 pop a
1710 ; 559 TIM1_SetIC4Prescaler(TIM1_ICPrescaler);
1712 0286 7b06 ld a,(OFST+6,sp)
1713 0288 cd06d8 call _TIM1_SetIC4Prescaler
1715 028b L746:
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