📄 stm8s_tim1.ls
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1 ; C Compiler for STM8 (COSMIC Software)
2 ; Parser V4.8.32.1 - 30 Mar 2010
3 ; Generator V4.3.4 - 23 Mar 2010
43 ; 69 void TIM1_DeInit(void)
43 ; 70 {
45 switch .text
46 0000 _TIM1_DeInit:
50 ; 71 TIM1->CR1 = TIM1_CR1_RESET_VALUE;
52 0000 725f5250 clr 21072
53 ; 72 TIM1->CR2 = TIM1_CR2_RESET_VALUE;
55 0004 725f5251 clr 21073
56 ; 73 TIM1->SMCR = TIM1_SMCR_RESET_VALUE;
58 0008 725f5252 clr 21074
59 ; 74 TIM1->ETR = TIM1_ETR_RESET_VALUE;
61 000c 725f5253 clr 21075
62 ; 75 TIM1->IER = TIM1_IER_RESET_VALUE;
64 0010 725f5254 clr 21076
65 ; 76 TIM1->SR2 = TIM1_SR2_RESET_VALUE;
67 0014 725f5256 clr 21078
68 ; 78 TIM1->CCER1 = TIM1_CCER1_RESET_VALUE;
70 0018 725f525c clr 21084
71 ; 79 TIM1->CCER2 = TIM1_CCER2_RESET_VALUE;
73 001c 725f525d clr 21085
74 ; 81 TIM1->CCMR1 = 0x01;
76 0020 35015258 mov 21080,#1
77 ; 82 TIM1->CCMR2 = 0x01;
79 0024 35015259 mov 21081,#1
80 ; 83 TIM1->CCMR3 = 0x01;
82 0028 3501525a mov 21082,#1
83 ; 84 TIM1->CCMR4 = 0x01;
85 002c 3501525b mov 21083,#1
86 ; 86 TIM1->CCER1 = TIM1_CCER1_RESET_VALUE;
88 0030 725f525c clr 21084
89 ; 87 TIM1->CCER2 = TIM1_CCER2_RESET_VALUE;
91 0034 725f525d clr 21085
92 ; 88 TIM1->CCMR1 = TIM1_CCMR1_RESET_VALUE;
94 0038 725f5258 clr 21080
95 ; 89 TIM1->CCMR2 = TIM1_CCMR2_RESET_VALUE;
97 003c 725f5259 clr 21081
98 ; 90 TIM1->CCMR3 = TIM1_CCMR3_RESET_VALUE;
100 0040 725f525a clr 21082
101 ; 91 TIM1->CCMR4 = TIM1_CCMR4_RESET_VALUE;
103 0044 725f525b clr 21083
104 ; 92 TIM1->CNTRH = TIM1_CNTRH_RESET_VALUE;
106 0048 725f525e clr 21086
107 ; 93 TIM1->CNTRL = TIM1_CNTRL_RESET_VALUE;
109 004c 725f525f clr 21087
110 ; 94 TIM1->PSCRH = TIM1_PSCRH_RESET_VALUE;
112 0050 725f5260 clr 21088
113 ; 95 TIM1->PSCRL = TIM1_PSCRL_RESET_VALUE;
115 0054 725f5261 clr 21089
116 ; 96 TIM1->ARRH = TIM1_ARRH_RESET_VALUE;
118 0058 35ff5262 mov 21090,#255
119 ; 97 TIM1->ARRL = TIM1_ARRL_RESET_VALUE;
121 005c 35ff5263 mov 21091,#255
122 ; 98 TIM1->CCR1H = TIM1_CCR1H_RESET_VALUE;
124 0060 725f5265 clr 21093
125 ; 99 TIM1->CCR1L = TIM1_CCR1L_RESET_VALUE;
127 0064 725f5266 clr 21094
128 ; 100 TIM1->CCR2H = TIM1_CCR2H_RESET_VALUE;
130 0068 725f5267 clr 21095
131 ; 101 TIM1->CCR2L = TIM1_CCR2L_RESET_VALUE;
133 006c 725f5268 clr 21096
134 ; 102 TIM1->CCR3H = TIM1_CCR3H_RESET_VALUE;
136 0070 725f5269 clr 21097
137 ; 103 TIM1->CCR3L = TIM1_CCR3L_RESET_VALUE;
139 0074 725f526a clr 21098
140 ; 104 TIM1->CCR4H = TIM1_CCR4H_RESET_VALUE;
142 0078 725f526b clr 21099
143 ; 105 TIM1->CCR4L = TIM1_CCR4L_RESET_VALUE;
145 007c 725f526c clr 21100
146 ; 106 TIM1->OISR = TIM1_OISR_RESET_VALUE;
148 0080 725f526f clr 21103
149 ; 107 TIM1->EGR = 0x01; /* TIM1_EGR_UG */
151 0084 35015257 mov 21079,#1
152 ; 108 TIM1->DTR = TIM1_DTR_RESET_VALUE;
154 0088 725f526e clr 21102
155 ; 109 TIM1->BKR = TIM1_BKR_RESET_VALUE;
157 008c 725f526d clr 21101
158 ; 110 TIM1->RCR = TIM1_RCR_RESET_VALUE;
160 0090 725f5264 clr 21092
161 ; 111 TIM1->SR1 = TIM1_SR1_RESET_VALUE;
163 0094 725f5255 clr 21077
164 ; 112 }
167 0098 81 ret
270 ; 135 void TIM1_TimeBaseInit(u16 TIM1_Prescaler,
270 ; 136 TIM1_CounterMode_TypeDef TIM1_CounterMode,
270 ; 137 u16 TIM1_Period,
270 ; 138 u8 TIM1_RepetitionCounter)
270 ; 139 {
271 switch .text
272 0099 _TIM1_TimeBaseInit:
274 0099 89 pushw x
275 00000000 OFST: set 0
278 ; 142 assert_param(IS_TIM1_COUNTER_MODE_OK(TIM1_CounterMode));
280 ; 145 TIM1->ARRH = (u8)(TIM1_Period >> 8);
282 009a 7b06 ld a,(OFST+6,sp)
283 009c c75262 ld 21090,a
284 ; 146 TIM1->ARRL = (u8)(TIM1_Period);
286 009f 7b07 ld a,(OFST+7,sp)
287 00a1 c75263 ld 21091,a
288 ; 149 TIM1->PSCRH = (u8)(TIM1_Prescaler >> 8);
290 00a4 9e ld a,xh
291 00a5 c75260 ld 21088,a
292 ; 150 TIM1->PSCRL = (u8)(TIM1_Prescaler);
294 00a8 9f ld a,xl
295 00a9 c75261 ld 21089,a
296 ; 153 TIM1->CR1 = (u8)(((TIM1->CR1) & (u8)(~(TIM1_CR1_CMS | TIM1_CR1_DIR))) | (u8)(TIM1_CounterMode));
298 00ac c65250 ld a,21072
299 00af a48f and a,#143
300 00b1 1a05 or a,(OFST+5,sp)
301 00b3 c75250 ld 21072,a
302 ; 156 TIM1->RCR = TIM1_RepetitionCounter;
304 00b6 7b08 ld a,(OFST+8,sp)
305 00b8 c75264 ld 21092,a
306 ; 158 }
309 00bb 85 popw x
310 00bc 81 ret
593 ; 189 void TIM1_OC1Init(TIM1_OCMode_TypeDef TIM1_OCMode,
593 ; 190 TIM1_OutputState_TypeDef TIM1_OutputState,
593 ; 191 TIM1_OutputNState_TypeDef TIM1_OutputNState,
593 ; 192 u16 TIM1_Pulse,
593 ; 193 TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
593 ; 194 TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
593 ; 195 TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
593 ; 196 TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
593 ; 197 {
594 switch .text
595 00bd _TIM1_OC1Init:
597 00bd 89 pushw x
598 00be 5203 subw sp,#3
599 00000003 OFST: set 3
602 ; 199 assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
604 ; 200 assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
606 ; 201 assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));
608 ; 202 assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
610 ; 203 assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
612 ; 204 assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
614 ; 205 assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));
616 ; 208 TIM1->CCER1 &= (u8)(~( TIM1_CCER1_CC1E | TIM1_CCER1_CC1NE | TIM1_CCER1_CC1P | TIM1_CCER1_CC1NP));
618 00c0 c6525c ld a,21084
619 00c3 a4f0 and a,#240
620 00c5 c7525c ld 21084,a
621 ; 210 TIM1->CCER1 |= (u8)((TIM1_OutputState & TIM1_CCER1_CC1E ) | (TIM1_OutputNState & TIM1_CCER1_CC1NE ) | (TIM1_OCPolarity & TIM1_CCER1_CC1P ) | (TIM1_OCNPolarity & TIM1_CCER1_CC1NP ));
623 00c8 7b0c ld a,(OFST+9,sp)
624 00ca a408 and a,#8
625 00cc 6b03 ld (OFST+0,sp),a
626 00ce 7b0b ld a,(OFST+8,sp)
627 00d0 a402 and a,#2
628 00d2 6b02 ld (OFST-1,sp),a
629 00d4 7b08 ld a,(OFST+5,sp)
630 00d6 a404 and a,#4
631 00d8 6b01 ld (OFST-2,sp),a
632 00da 9f ld a,xl
633 00db a401 and a,#1
634 00dd 1a01 or a,(OFST-2,sp)
635 00df 1a02 or a,(OFST-1,sp)
636 00e1 1a03 or a,(OFST+0,sp)
637 00e3 ca525c or a,21084
638 00e6 c7525c ld 21084,a
639 ; 213 TIM1->CCMR1 = (u8)((TIM1->CCMR1 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_OCMode);
641 00e9 c65258 ld a,21080
642 00ec a48f and a,#143
643 00ee 1a04 or a,(OFST+1,sp)
644 00f0 c75258 ld 21080,a
645 ; 216 TIM1->OISR &= (u8)(~(TIM1_OISR_OIS1 | TIM1_OISR_OIS1N));
647 00f3 c6526f ld a,21103
648 00f6 a4fc and a,#252
649 00f8 c7526f ld 21103,a
650 ; 218 TIM1->OISR |= (u8)(( TIM1_OCIdleState & TIM1_OISR_OIS1 ) | ( TIM1_OCNIdleState & TIM1_OISR_OIS1N ));
652 00fb 7b0e ld a,(OFST+11,sp)
653 00fd a402 and a,#2
654 00ff 6b03 ld (OFST+0,sp),a
655 0101 7b0d ld a,(OFST+10,sp)
656 0103 a401 and a,#1
657 0105 1a03 or a,(OFST+0,sp)
658 0107 ca526f or a,21103
659 010a c7526f ld 21103,a
660 ; 221 TIM1->CCR1H = (u8)(TIM1_Pulse >> 8);
662 010d 7b09 ld a,(OFST+6,sp)
663 010f c75265 ld 21093,a
664 ; 222 TIM1->CCR1L = (u8)(TIM1_Pulse);
666 0112 7b0a ld a,(OFST+7,sp)
667 0114 c75266 ld 21094,a
668 ; 223 }
671 0117 5b05 addw sp,#5
672 0119 81 ret
774 ; 254 void TIM1_OC2Init(TIM1_OCMode_TypeDef TIM1_OCMode,
774 ; 255 TIM1_OutputState_TypeDef TIM1_OutputState,
774 ; 256 TIM1_OutputNState_TypeDef TIM1_OutputNState,
774 ; 257 u16 TIM1_Pulse,
774 ; 258 TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
774 ; 259 TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
774 ; 260 TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
774 ; 261 TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
774 ; 262 {
775 switch .text
776 011a _TIM1_OC2Init:
778 011a 89 pushw x
779 011b 5203 subw sp,#3
780 00000003 OFST: set 3
783 ; 266 assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
785 ; 267 assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
787 ; 268 assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));
789 ; 269 assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
791 ; 270 assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
793 ; 271 assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
795 ; 272 assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));
797 ; 275 TIM1->CCER1 &= (u8)(~( TIM1_CCER1_CC2E | TIM1_CCER1_CC2NE | TIM1_CCER1_CC2P | TIM1_CCER1_CC2NP));
799 011d c6525c ld a,21084
800 0120 a40f and a,#15
801 0122 c7525c ld 21084,a
802 ; 277 TIM1->CCER1 |= (u8)((TIM1_OutputState & TIM1_CCER1_CC2E ) | (TIM1_OutputNState & TIM1_CCER1_CC2NE ) | (TIM1_OCPolarity & TIM1_CCER1_CC2P ) | (TIM1_OCNPolarity & TIM1_CCER1_CC2NP ));
804 0125 7b0c ld a,(OFST+9,sp)
805 0127 a480 and a,#128
806 0129 6b03 ld (OFST+0,sp),a
807 012b 7b0b ld a,(OFST+8,sp)
808 012d a420 and a,#32
809 012f 6b02 ld (OFST-1,sp),a
810 0131 7b08 ld a,(OFST+5,sp)
811 0133 a440 and a,#64
812 0135 6b01 ld (OFST-2,sp),a
813 0137 9f ld a,xl
814 0138 a410 and a,#16
815 013a 1a01 or a,(OFST-2,sp)
816 013c 1a02 or a,(OFST-1,sp)
817 013e 1a03 or a,(OFST+0,sp)
818 0140 ca525c or a,21084
819 0143 c7525c ld 21084,a
820 ; 281 TIM1->CCMR2 = (u8)((TIM1->CCMR2 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_OCMode);
822 0146 c65259 ld a,21081
823 0149 a48f and a,#143
824 014b 1a04 or a,(OFST+1,sp)
825 014d c75259 ld 21081,a
826 ; 284 TIM1->OISR &= (u8)(~(TIM1_OISR_OIS2 | TIM1_OISR_OIS2N));
828 0150 c6526f ld a,21103
829 0153 a4f3 and a,#243
830 0155 c7526f ld 21103,a
831 ; 286 TIM1->OISR |= (u8)((TIM1_OISR_OIS2 & TIM1_OCIdleState) | (TIM1_OISR_OIS2N & TIM1_OCNIdleState));
833 0158 7b0e ld a,(OFST+11,sp)
834 015a a408 and a,#8
835 015c 6b03 ld (OFST+0,sp),a
836 015e 7b0d ld a,(OFST+10,sp)
837 0160 a404 and a,#4
838 0162 1a03 or a,(OFST+0,sp)
839 0164 ca526f or a,21103
840 0167 c7526f ld 21103,a
841 ; 289 TIM1->CCR2H = (u8)(TIM1_Pulse >> 8);
843 016a 7b09 ld a,(OFST+6,sp)
844 016c c75267 ld 21095,a
845 ; 290 TIM1->CCR2L = (u8)(TIM1_Pulse);
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