📄 stm8s_uart1.ls
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1817 ; 691 UART1->CR4 &= ((u8)~UART1_CR4_ADD);
1819 02ae c65237 ld a,21047
1820 02b1 a4f0 and a,#240
1821 02b3 c75237 ld 21047,a
1822 ; 693 UART1->CR4 |= UART1_Address;
1824 02b6 c65237 ld a,21047
1825 02b9 1a01 or a,(OFST+1,sp)
1826 02bb c75237 ld 21047,a
1827 ; 694 }
1830 02be 84 pop a
1831 02bf 81 ret
1863 ; 713 void UART1_SetGuardTime(u8 UART1_GuardTime)
1863 ; 714 {
1864 switch .text
1865 02c0 _UART1_SetGuardTime:
1869 ; 716 UART1->GTR = UART1_GuardTime;
1871 02c0 c75239 ld 21049,a
1872 ; 717 }
1875 02c3 81 ret
1907 ; 751 void UART1_SetPrescaler(u8 UART1_Prescaler)
1907 ; 752 {
1908 switch .text
1909 02c4 _UART1_SetPrescaler:
1913 ; 754 UART1->PSCR = UART1_Prescaler;
1915 02c4 c7523a ld 21050,a
1916 ; 755 }
1919 02c7 81 ret
2062 ; 775 FlagStatus UART1_GetFlagStatus(UART1_Flag_TypeDef UART1_FLAG)
2062 ; 776 {
2063 switch .text
2064 02c8 _UART1_GetFlagStatus:
2066 02c8 89 pushw x
2067 02c9 88 push a
2068 00000001 OFST: set 1
2071 ; 777 FlagStatus status = RESET;
2073 ; 780 assert_param(IS_UART1_FLAG_OK(UART1_FLAG));
2075 ; 784 if (UART1_FLAG == UART1_FLAG_LBDF)
2077 02ca a30210 cpw x,#528
2078 02cd 2610 jrne L1301
2079 ; 786 if ((UART1->CR4 & (u8)UART1_FLAG) != (u8)0x00)
2081 02cf 9f ld a,xl
2082 02d0 c45237 and a,21047
2083 02d3 2706 jreq L3301
2084 ; 789 status = SET;
2086 02d5 a601 ld a,#1
2087 02d7 6b01 ld (OFST+0,sp),a
2089 02d9 202b jra L7301
2090 02db L3301:
2091 ; 794 status = RESET;
2093 02db 0f01 clr (OFST+0,sp)
2094 02dd 2027 jra L7301
2095 02df L1301:
2096 ; 797 else if (UART1_FLAG == UART1_FLAG_SBK)
2098 02df 1e02 ldw x,(OFST+1,sp)
2099 02e1 a30101 cpw x,#257
2100 02e4 2611 jrne L1401
2101 ; 799 if ((UART1->CR2 & (u8)UART1_FLAG) != (u8)0x00)
2103 02e6 c65235 ld a,21045
2104 02e9 1503 bcp a,(OFST+2,sp)
2105 02eb 2706 jreq L3401
2106 ; 802 status = SET;
2108 02ed a601 ld a,#1
2109 02ef 6b01 ld (OFST+0,sp),a
2111 02f1 2013 jra L7301
2112 02f3 L3401:
2113 ; 807 status = RESET;
2115 02f3 0f01 clr (OFST+0,sp)
2116 02f5 200f jra L7301
2117 02f7 L1401:
2118 ; 812 if ((UART1->SR & (u8)UART1_FLAG) != (u8)0x00)
2120 02f7 c65230 ld a,21040
2121 02fa 1503 bcp a,(OFST+2,sp)
2122 02fc 2706 jreq L1501
2123 ; 815 status = SET;
2125 02fe a601 ld a,#1
2126 0300 6b01 ld (OFST+0,sp),a
2128 0302 2002 jra L7301
2129 0304 L1501:
2130 ; 820 status = RESET;
2132 0304 0f01 clr (OFST+0,sp)
2133 0306 L7301:
2134 ; 824 return status;
2136 0306 7b01 ld a,(OFST+0,sp)
2139 0308 5b03 addw sp,#3
2140 030a 81 ret
2175 ; 859 void UART1_ClearFlag(UART1_Flag_TypeDef UART1_FLAG)
2175 ; 860 {
2176 switch .text
2177 030b _UART1_ClearFlag:
2181 ; 861 assert_param(IS_UART1_CLEAR_FLAG_OK(UART1_FLAG));
2183 ; 864 if (UART1_FLAG == UART1_FLAG_RXNE)
2185 030b a30020 cpw x,#32
2186 030e 2606 jrne L3701
2187 ; 866 UART1->SR = (u8)~(UART1_SR_RXNE);
2189 0310 35df5230 mov 21040,#223
2191 0314 2004 jra L5701
2192 0316 L3701:
2193 ; 871 UART1->CR4 &= (u8)~(UART1_CR4_LBDF);
2195 0316 72195237 bres 21047,#4
2196 031a L5701:
2197 ; 873 }
2200 031a 81 ret
2274 ; 900 ITStatus UART1_GetITStatus(UART1_IT_TypeDef UART1_IT)
2274 ; 901 {
2275 switch .text
2276 031b _UART1_GetITStatus:
2278 031b 89 pushw x
2279 031c 89 pushw x
2280 00000002 OFST: set 2
2283 ; 902 ITStatus pendingbitstatus = RESET;
2285 ; 903 u8 itpos = 0;
2287 ; 904 u8 itmask1 = 0;
2289 ; 905 u8 itmask2 = 0;
2291 ; 906 u8 enablestatus = 0;
2293 ; 909 assert_param(IS_UART1_GET_IT_OK(UART1_IT));
2295 ; 912 itpos = (u8)((u8)1 << (u8)((u8)UART1_IT & (u8)0x0F));
2297 031d 9f ld a,xl
2298 031e a40f and a,#15
2299 0320 5f clrw x
2300 0321 97 ld xl,a
2301 0322 a601 ld a,#1
2302 0324 5d tnzw x
2303 0325 2704 jreq L27
2304 0327 L47:
2305 0327 48 sll a
2306 0328 5a decw x
2307 0329 26fc jrne L47
2308 032b L27:
2309 032b 6b01 ld (OFST-1,sp),a
2310 ; 914 itmask1 = (u8)((u8)UART1_IT >> (u8)4);
2312 032d 7b04 ld a,(OFST+2,sp)
2313 032f 4e swap a
2314 0330 a40f and a,#15
2315 0332 6b02 ld (OFST+0,sp),a
2316 ; 916 itmask2 = (u8)((u8)1 << itmask1);
2318 0334 7b02 ld a,(OFST+0,sp)
2319 0336 5f clrw x
2320 0337 97 ld xl,a
2321 0338 a601 ld a,#1
2322 033a 5d tnzw x
2323 033b 2704 jreq L67
2324 033d L001:
2325 033d 48 sll a
2326 033e 5a decw x
2327 033f 26fc jrne L001
2328 0341 L67:
2329 0341 6b02 ld (OFST+0,sp),a
2330 ; 920 if (UART1_IT == UART1_IT_PE)
2332 0343 1e03 ldw x,(OFST+1,sp)
2333 0345 a30100 cpw x,#256
2334 0348 261c jrne L1311
2335 ; 923 enablestatus = (u8)((u8)UART1->CR1 & itmask2);
2337 034a c65234 ld a,21044
2338 034d 1402 and a,(OFST+0,sp)
2339 034f 6b02 ld (OFST+0,sp),a
2340 ; 926 if (((UART1->SR & itpos) != (u8)0x00) && enablestatus)
2342 0351 c65230 ld a,21040
2343 0354 1501 bcp a,(OFST-1,sp)
2344 0356 270a jreq L3311
2346 0358 0d02 tnz (OFST+0,sp)
2347 035a 2706 jreq L3311
2348 ; 929 pendingbitstatus = SET;
2350 035c a601 ld a,#1
2351 035e 6b02 ld (OFST+0,sp),a
2353 0360 2041 jra L7311
2354 0362 L3311:
2355 ; 934 pendingbitstatus = RESET;
2357 0362 0f02 clr (OFST+0,sp)
2358 0364 203d jra L7311
2359 0366 L1311:
2360 ; 938 else if (UART1_IT == UART1_IT_LBDF)
2362 0366 1e03 ldw x,(OFST+1,sp)
2363 0368 a30346 cpw x,#838
2364 036b 261c jrne L1411
2365 ; 941 enablestatus = (u8)((u8)UART1->CR4 & itmask2);
2367 036d c65237 ld a,21047
2368 0370 1402 and a,(OFST+0,sp)
2369 0372 6b02 ld (OFST+0,sp),a
2370 ; 943 if (((UART1->CR4 & itpos) != (u8)0x00) && enablestatus)
2372 0374 c65237 ld a,21047
2373 0377 1501 bcp a,(OFST-1,sp)
2374 0379 270a jreq L3411
2376 037b 0d02 tnz (OFST+0,sp)
2377 037d 2706 jreq L3411
2378 ; 946 pendingbitstatus = SET;
2380 037f a601 ld a,#1
2381 0381 6b02 ld (OFST+0,sp),a
2383 0383 201e jra L7311
2384 0385 L3411:
2385 ; 951 pendingbitstatus = RESET;
2387 0385 0f02 clr (OFST+0,sp)
2388 0387 201a jra L7311
2389 0389 L1411:
2390 ; 957 enablestatus = (u8)((u8)UART1->CR2 & itmask2);
2392 0389 c65235 ld a,21045
2393 038c 1402 and a,(OFST+0,sp)
2394 038e 6b02 ld (OFST+0,sp),a
2395 ; 959 if (((UART1->SR & itpos) != (u8)0x00) && enablestatus)
2397 0390 c65230 ld a,21040
2398 0393 1501 bcp a,(OFST-1,sp)
2399 0395 270a jreq L1511
2401 0397 0d02 tnz (OFST+0,sp)
2402 0399 2706 jreq L1511
2403 ; 962 pendingbitstatus = SET;
2405 039b a601 ld a,#1
2406 039d 6b02 ld (OFST+0,sp),a
2408 039f 2002 jra L7311
2409 03a1 L1511:
2410 ; 967 pendingbitstatus = RESET;
2412 03a1 0f02 clr (OFST+0,sp)
2413 03a3 L7311:
2414 ; 972 return pendingbitstatus;
2416 03a3 7b02 ld a,(OFST+0,sp)
2419 03a5 5b04 addw sp,#4
2420 03a7 81 ret
2456 ; 1006 void UART1_ClearITPendingBit(UART1_IT_TypeDef UART1_IT)
2456 ; 1007 {
2457 switch .text
2458 03a8 _UART1_ClearITPendingBit:
2462 ; 1008 assert_param(IS_UART1_CLEAR_FLAG_OK(UART1_IT));
2464 ; 1011 if (UART1_IT == UART1_IT_RXNE)
2466 03a8 a30255 cpw x,#597
2467 03ab 2606 jrne L3711
2468 ; 1013 UART1->SR = (u8)~(UART1_SR_RXNE);
2470 03ad 35df5230 mov 21040,#223
2472 03b1 2004 jra L5711
2473 03b3 L3711:
2474 ; 1018 UART1->CR4 &= (u8)~(UART1_CR4_LBDF);
2476 03b3 72195237 bres 21047,#4
2477 03b7 L5711:
2478 ; 1020 }
2481 03b7 81 ret
2494 xref _CLK_GetClockFreq
2495 xdef _UART1_ClearITPendingBit
2496 xdef _UART1_GetITStatus
2497 xdef _UART1_ClearFlag
2498 xdef _UART1_GetFlagStatus
2499 xdef _UART1_SetPrescaler
2500 xdef _UART1_SetGuardTime
2501 xdef _UART1_SetAddress
2502 xdef _UART1_SendBreak
2503 xdef _UART1_SendData9
2504 xdef _UART1_SendData8
2505 xdef _UART1_ReceiveData9
2506 xdef _UART1_ReceiveData8
2507 xdef _UART1_ReceiverWakeUpCmd
2508 xdef _UART1_WakeUpConfig
2509 xdef _UART1_SmartCardNACKCmd
2510 xdef _UART1_SmartCardCmd
2511 xdef _UART1_LINCmd
2512 xdef _UART1_LINBreakDetectionConfig
2513 xdef _UART1_IrDACmd
2514 xdef _UART1_IrDAConfig
2515 xdef _UART1_HalfDuplexCmd
2516 xdef _UART1_ITConfig
2517 xdef _UART1_Cmd
2518 xdef _UART1_Init
2519 xdef _UART1_DeInit
2520 xref.b c_lreg
2521 xref.b c_x
2540 xref c_lursh
2541 xref c_lsub
2542 xref c_smul
2543 xref c_ludv
2544 xref c_rtol
2545 xref c_llsh
2546 xref c_ltor
2547 end
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