📄 stm8s_uart1.ls
字号:
889 ; 251 UART1->CR2 |= itpos;
891 01aa c65235 ld a,21045
892 01ad 1a02 or a,(OFST+0,sp)
893 01af c75235 ld 21045,a
895 01b2 2035 jra L323
896 01b4 L713:
897 ; 255 UART1->CR4 |= itpos;
899 01b4 c65237 ld a,21047
900 01b7 1a02 or a,(OFST+0,sp)
901 01b9 c75237 ld 21047,a
902 01bc 202b jra L323
903 01be L113:
904 ; 261 if (uartreg == 0x01)
906 01be 7b01 ld a,(OFST-1,sp)
907 01c0 a101 cp a,#1
908 01c2 260b jrne L523
909 ; 263 UART1->CR1 &= (u8)(~itpos);
911 01c4 7b02 ld a,(OFST+0,sp)
912 01c6 43 cpl a
913 01c7 c45234 and a,21044
914 01ca c75234 ld 21044,a
916 01cd 201a jra L323
917 01cf L523:
918 ; 265 else if (uartreg == 0x02)
920 01cf 7b01 ld a,(OFST-1,sp)
921 01d1 a102 cp a,#2
922 01d3 260b jrne L133
923 ; 267 UART1->CR2 &= (u8)(~itpos);
925 01d5 7b02 ld a,(OFST+0,sp)
926 01d7 43 cpl a
927 01d8 c45235 and a,21045
928 01db c75235 ld 21045,a
930 01de 2009 jra L323
931 01e0 L133:
932 ; 271 UART1->CR4 &= (u8)(~itpos);
934 01e0 7b02 ld a,(OFST+0,sp)
935 01e2 43 cpl a
936 01e3 c45237 and a,21047
937 01e6 c75237 ld 21047,a
938 01e9 L323:
939 ; 275 }
942 01e9 5b04 addw sp,#4
943 01eb 81 ret
979 ; 292 void UART1_HalfDuplexCmd(FunctionalState NewState)
979 ; 293 {
980 switch .text
981 01ec _UART1_HalfDuplexCmd:
985 ; 294 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
987 ; 296 if (NewState != DISABLE)
989 01ec 4d tnz a
990 01ed 2706 jreq L353
991 ; 298 UART1->CR5 |= UART1_CR5_HDSEL; /**< UART1 Half Duplex Enable */
993 01ef 72165238 bset 21048,#3
995 01f3 2004 jra L553
996 01f5 L353:
997 ; 302 UART1->CR5 &= (u8)~UART1_CR5_HDSEL; /**< UART1 Half Duplex Disable */
999 01f5 72175238 bres 21048,#3
1000 01f9 L553:
1001 ; 304 }
1004 01f9 81 ret
1061 ; 323 void UART1_IrDAConfig(UART1_IrDAMode_TypeDef UART1_IrDAMode)
1061 ; 324 {
1062 switch .text
1063 01fa _UART1_IrDAConfig:
1067 ; 325 assert_param(IS_UART1_IRDAMODE_OK(UART1_IrDAMode));
1069 ; 327 if (UART1_IrDAMode != UART1_IRDAMODE_NORMAL)
1071 01fa 4d tnz a
1072 01fb 2706 jreq L504
1073 ; 329 UART1->CR5 |= UART1_CR5_IRLP;
1075 01fd 72145238 bset 21048,#2
1077 0201 2004 jra L704
1078 0203 L504:
1079 ; 333 UART1->CR5 &= ((u8)~UART1_CR5_IRLP);
1081 0203 72155238 bres 21048,#2
1082 0207 L704:
1083 ; 335 }
1086 0207 81 ret
1121 ; 354 void UART1_IrDACmd(FunctionalState NewState)
1121 ; 355 {
1122 switch .text
1123 0208 _UART1_IrDACmd:
1127 ; 358 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1129 ; 360 if (NewState != DISABLE)
1131 0208 4d tnz a
1132 0209 2706 jreq L724
1133 ; 363 UART1->CR5 |= UART1_CR5_IREN;
1135 020b 72125238 bset 21048,#1
1137 020f 2004 jra L134
1138 0211 L724:
1139 ; 368 UART1->CR5 &= ((u8)~UART1_CR5_IREN);
1141 0211 72135238 bres 21048,#1
1142 0215 L134:
1143 ; 370 }
1146 0215 81 ret
1205 ; 388 void UART1_LINBreakDetectionConfig(UART1_LINBreakDetectionLength_TypeDef UART1_LINBreakDetectionLength)
1205 ; 389 {
1206 switch .text
1207 0216 _UART1_LINBreakDetectionConfig:
1211 ; 390 assert_param(IS_UART1_LINBREAKDETECTIONLENGTH_OK(UART1_LINBreakDetectionLength));
1213 ; 392 if (UART1_LINBreakDetectionLength != UART1_LINBREAKDETECTIONLENGTH_10BITS)
1215 0216 4d tnz a
1216 0217 2706 jreq L164
1217 ; 394 UART1->CR4 |= UART1_CR4_LBDL;
1219 0219 721a5237 bset 21047,#5
1221 021d 2004 jra L364
1222 021f L164:
1223 ; 398 UART1->CR4 &= ((u8)~UART1_CR4_LBDL);
1225 021f 721b5237 bres 21047,#5
1226 0223 L364:
1227 ; 400 }
1230 0223 81 ret
1265 ; 418 void UART1_LINCmd(FunctionalState NewState)
1265 ; 419 {
1266 switch .text
1267 0224 _UART1_LINCmd:
1271 ; 420 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1273 ; 422 if (NewState != DISABLE)
1275 0224 4d tnz a
1276 0225 2706 jreq L305
1277 ; 425 UART1->CR3 |= UART1_CR3_LINEN;
1279 0227 721c5236 bset 21046,#6
1281 022b 2004 jra L505
1282 022d L305:
1283 ; 430 UART1->CR3 &= ((u8)~UART1_CR3_LINEN);
1285 022d 721d5236 bres 21046,#6
1286 0231 L505:
1287 ; 432 }
1290 0231 81 ret
1325 ; 451 void UART1_SmartCardCmd(FunctionalState NewState)
1325 ; 452 {
1326 switch .text
1327 0232 _UART1_SmartCardCmd:
1331 ; 453 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1333 ; 455 if (NewState != DISABLE)
1335 0232 4d tnz a
1336 0233 2706 jreq L525
1337 ; 458 UART1->CR5 |= UART1_CR5_SCEN;
1339 0235 721a5238 bset 21048,#5
1341 0239 2004 jra L725
1342 023b L525:
1343 ; 463 UART1->CR5 &= ((u8)(~UART1_CR5_SCEN));
1345 023b 721b5238 bres 21048,#5
1346 023f L725:
1347 ; 465 }
1350 023f 81 ret
1386 ; 485 void UART1_SmartCardNACKCmd(FunctionalState NewState)
1386 ; 486 {
1387 switch .text
1388 0240 _UART1_SmartCardNACKCmd:
1392 ; 487 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1394 ; 489 if (NewState != DISABLE)
1396 0240 4d tnz a
1397 0241 2706 jreq L745
1398 ; 492 UART1->CR5 |= UART1_CR5_NACK;
1400 0243 72185238 bset 21048,#4
1402 0247 2004 jra L155
1403 0249 L745:
1404 ; 497 UART1->CR5 &= ((u8)~(UART1_CR5_NACK));
1406 0249 72195238 bres 21048,#4
1407 024d L155:
1408 ; 499 }
1411 024d 81 ret
1468 ; 518 void UART1_WakeUpConfig(UART1_WakeUp_TypeDef UART1_WakeUp)
1468 ; 519 {
1469 switch .text
1470 024e _UART1_WakeUpConfig:
1474 ; 520 assert_param(IS_UART1_WAKEUP_OK(UART1_WakeUp));
1476 ; 522 UART1->CR1 &= ((u8)~UART1_CR1_WAKE);
1478 024e 72175234 bres 21044,#3
1479 ; 523 UART1->CR1 |= (u8)UART1_WakeUp;
1481 0252 ca5234 or a,21044
1482 0255 c75234 ld 21044,a
1483 ; 524 }
1486 0258 81 ret
1522 ; 541 void UART1_ReceiverWakeUpCmd(FunctionalState NewState)
1522 ; 542 {
1523 switch .text
1524 0259 _UART1_ReceiverWakeUpCmd:
1528 ; 543 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1530 ; 545 if (NewState != DISABLE)
1532 0259 4d tnz a
1533 025a 2706 jreq L716
1534 ; 548 UART1->CR2 |= UART1_CR2_RWU;
1536 025c 72125235 bset 21045,#1
1538 0260 2004 jra L126
1539 0262 L716:
1540 ; 553 UART1->CR2 &= ((u8)~UART1_CR2_RWU);
1542 0262 72135235 bres 21045,#1
1543 0266 L126:
1544 ; 555 }
1547 0266 81 ret
1570 ; 572 u8 UART1_ReceiveData8(void)
1570 ; 573 {
1571 switch .text
1572 0267 _UART1_ReceiveData8:
1576 ; 574 return ((u8)UART1->DR);
1578 0267 c65231 ld a,21041
1581 026a 81 ret
1604 ; 593 u16 UART1_ReceiveData9(void)
1604 ; 594 {
1605 switch .text
1606 026b _UART1_ReceiveData9:
1608 026b 89 pushw x
1609 00000002 OFST: set 2
1612 ; 595 return (u16)( (((u16) UART1->DR) | ((u16)(((u16)( (u16)UART1->CR1 & (u16)UART1_CR1_R8)) << 1))) & ((u16)0x01FF));
1614 026c c65234 ld a,21044
1615 026f 5f clrw x
1616 0270 a480 and a,#128
1617 0272 5f clrw x
1618 0273 02 rlwa x,a
1619 0274 58 sllw x
1620 0275 1f01 ldw (OFST-1,sp),x
1621 0277 c65231 ld a,21041
1622 027a 5f clrw x
1623 027b 97 ld xl,a
1624 027c 01 rrwa x,a
1625 027d 1a02 or a,(OFST+0,sp)
1626 027f 01 rrwa x,a
1627 0280 1a01 or a,(OFST-1,sp)
1628 0282 01 rrwa x,a
1629 0283 01 rrwa x,a
1630 0284 a4ff and a,#255
1631 0286 01 rrwa x,a
1632 0287 a401 and a,#1
1633 0289 01 rrwa x,a
1636 028a 5b02 addw sp,#2
1637 028c 81 ret
1669 ; 615 void UART1_SendData8(u8 Data)
1669 ; 616 {
1670 switch .text
1671 028d _UART1_SendData8:
1675 ; 618 UART1->DR = Data;
1677 028d c75231 ld 21041,a
1678 ; 619 }
1681 0290 81 ret
1713 ; 638 void UART1_SendData9(u16 Data)
1713 ; 639 {
1714 switch .text
1715 0291 _UART1_SendData9:
1717 0291 89 pushw x
1718 00000000 OFST: set 0
1721 ; 641 UART1->CR1 &= ((u8)~UART1_CR1_T8);
1723 0292 721d5234 bres 21044,#6
1724 ; 643 UART1->CR1 |= (u8)(((u8)(Data >> 2)) & UART1_CR1_T8);
1726 0296 54 srlw x
1727 0297 54 srlw x
1728 0298 9f ld a,xl
1729 0299 a440 and a,#64
1730 029b ca5234 or a,21044
1731 029e c75234 ld 21044,a
1732 ; 645 UART1->DR = (u8)(Data);
1734 02a1 7b02 ld a,(OFST+2,sp)
1735 02a3 c75231 ld 21041,a
1736 ; 646 }
1739 02a6 85 popw x
1740 02a7 81 ret
1763 ; 662 void UART1_SendBreak(void)
1763 ; 663 {
1764 switch .text
1765 02a8 _UART1_SendBreak:
1769 ; 664 UART1->CR2 |= UART1_CR2_SBK;
1771 02a8 72105235 bset 21045,#0
1772 ; 665 }
1775 02ac 81 ret
1807 ; 685 void UART1_SetAddress(u8 UART1_Address)
1807 ; 686 {
1808 switch .text
1809 02ad _UART1_SetAddress:
1811 02ad 88 push a
1812 00000000 OFST: set 0
1815 ; 688 assert_param(IS_UART1_ADDRESS_OK(UART1_Address));
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