📄 stm8s_uart1.ls
字号:
1 ; C Compiler for STM8 (COSMIC Software)
2 ; Parser V4.8.32.1 - 30 Mar 2010
3 ; Generator V4.3.4 - 23 Mar 2010
52 ; 64 void UART1_DeInit(void)
52 ; 65 {
54 switch .text
55 0000 _UART1_DeInit:
57 0000 88 push a
58 00000001 OFST: set 1
61 ; 66 u8 dummy = 0;
63 ; 70 dummy = UART1->SR;
65 0001 c65230 ld a,21040
66 ; 71 dummy = UART1->DR;
68 0004 c65231 ld a,21041
69 ; 73 UART1->BRR2 = UART1_BRR2_RESET_VALUE; /*< Set UART1_BRR2 to reset value 0x00 */
71 0007 725f5233 clr 21043
72 ; 74 UART1->BRR1 = UART1_BRR1_RESET_VALUE; /*< Set UART1_BRR1 to reset value 0x00 */
74 000b 725f5232 clr 21042
75 ; 76 UART1->CR1 = UART1_CR1_RESET_VALUE; /*< Set UART1_CR1 to reset value 0x00 */
77 000f 725f5234 clr 21044
78 ; 77 UART1->CR2 = UART1_CR2_RESET_VALUE; /*< Set UART1_CR2 to reset value 0x00 */
80 0013 725f5235 clr 21045
81 ; 78 UART1->CR3 = UART1_CR3_RESET_VALUE; /*< Set UART1_CR3 to reset value 0x00 */
83 0017 725f5236 clr 21046
84 ; 79 UART1->CR4 = UART1_CR4_RESET_VALUE; /*< Set UART1_CR4 to reset value 0x00 */
86 001b 725f5237 clr 21047
87 ; 80 UART1->CR5 = UART1_CR5_RESET_VALUE; /*< Set UART1_CR5 to reset value 0x00 */
89 001f 725f5238 clr 21048
90 ; 82 UART1->GTR = UART1_GTR_RESET_VALUE;
92 0023 725f5239 clr 21049
93 ; 83 UART1->PSCR = UART1_PSCR_RESET_VALUE;
95 0027 725f523a clr 21050
96 ; 84 }
99 002b 84 pop a
100 002c 81 ret
397 .const: section .text
398 0000 L01:
399 0000 00000064 dc.l 100
400 ; 104 void UART1_Init(u32 BaudRate, UART1_WordLength_TypeDef WordLength, UART1_StopBits_TypeDef StopBits, UART1_Parity_TypeDef Parity, UART1_SyncMode_TypeDef SyncMode, UART1_Mode_TypeDef Mode)
400 ; 105 {
401 switch .text
402 002d _UART1_Init:
404 002d 520c subw sp,#12
405 0000000c OFST: set 12
408 ; 106 u32 BaudRate_Mantissa, BaudRate_Mantissa100 = 0;
410 ; 109 assert_param(IS_UART1_BAUDRATE_OK(BaudRate));
412 ; 111 assert_param(IS_UART1_WORDLENGTH_OK(WordLength));
414 ; 113 assert_param(IS_UART1_STOPBITS_OK(StopBits));
416 ; 115 assert_param(IS_UART1_PARITY_OK(Parity));
418 ; 118 assert_param(IS_UART1_MODE_OK((u8)Mode));
420 ; 122 assert_param(IS_UART1_SYNCMODE_OK((u8)SyncMode));
422 ; 124 UART1->CR1 &= (u8)(~UART1_CR1_M); /**< Clear the word length bit */
424 002f 72195234 bres 21044,#4
425 ; 125 UART1->CR1 |= (u8)WordLength; /**< Set the word length bit according to UART1_WordLength value */
427 0033 c65234 ld a,21044
428 0036 1a13 or a,(OFST+7,sp)
429 0038 c75234 ld 21044,a
430 ; 127 UART1->CR3 &= (u8)(~UART1_CR3_STOP); /**< Clear the STOP bits */
432 003b c65236 ld a,21046
433 003e a4cf and a,#207
434 0040 c75236 ld 21046,a
435 ; 128 UART1->CR3 |= (u8)StopBits; /**< Set the STOP bits number according to UART1_StopBits value */
437 0043 c65236 ld a,21046
438 0046 1a14 or a,(OFST+8,sp)
439 0048 c75236 ld 21046,a
440 ; 130 UART1->CR1 &= (u8)(~(UART1_CR1_PCEN | UART1_CR1_PS )); /**< Clear the Parity Control bit */
442 004b c65234 ld a,21044
443 004e a4f9 and a,#249
444 0050 c75234 ld 21044,a
445 ; 131 UART1->CR1 |= (u8)Parity; /**< Set the Parity Control bit to UART1_Parity value */
447 0053 c65234 ld a,21044
448 0056 1a15 or a,(OFST+9,sp)
449 0058 c75234 ld 21044,a
450 ; 133 UART1->BRR1 &= (u8)(~UART1_BRR1_DIVM); /**< Clear the LSB mantissa of UART1DIV */
452 005b 725f5232 clr 21042
453 ; 134 UART1->BRR2 &= (u8)(~UART1_BRR2_DIVM); /**< Clear the MSB mantissa of UART1DIV */
455 005f c65233 ld a,21043
456 0062 a40f and a,#15
457 0064 c75233 ld 21043,a
458 ; 135 UART1->BRR2 &= (u8)(~UART1_BRR2_DIVF); /**< Clear the Fraction bits of UART1DIV */
460 0067 c65233 ld a,21043
461 006a a4f0 and a,#240
462 006c c75233 ld 21043,a
463 ; 138 BaudRate_Mantissa = ((u32)CLK_GetClockFreq() / (BaudRate << 4));
465 006f 96 ldw x,sp
466 0070 1c000f addw x,#OFST+3
467 0073 cd0000 call c_ltor
469 0076 a604 ld a,#4
470 0078 cd0000 call c_llsh
472 007b 96 ldw x,sp
473 007c 1c0001 addw x,#OFST-11
474 007f cd0000 call c_rtol
476 0082 cd0000 call _CLK_GetClockFreq
478 0085 96 ldw x,sp
479 0086 1c0001 addw x,#OFST-11
480 0089 cd0000 call c_ludv
482 008c 96 ldw x,sp
483 008d 1c0009 addw x,#OFST-3
484 0090 cd0000 call c_rtol
486 ; 139 BaudRate_Mantissa100 = (((u32)CLK_GetClockFreq() * 100) / (BaudRate << 4));
488 0093 96 ldw x,sp
489 0094 1c000f addw x,#OFST+3
490 0097 cd0000 call c_ltor
492 009a a604 ld a,#4
493 009c cd0000 call c_llsh
495 009f 96 ldw x,sp
496 00a0 1c0001 addw x,#OFST-11
497 00a3 cd0000 call c_rtol
499 00a6 cd0000 call _CLK_GetClockFreq
501 00a9 a664 ld a,#100
502 00ab cd0000 call c_smul
504 00ae 96 ldw x,sp
505 00af 1c0001 addw x,#OFST-11
506 00b2 cd0000 call c_ludv
508 00b5 96 ldw x,sp
509 00b6 1c0005 addw x,#OFST-7
510 00b9 cd0000 call c_rtol
512 ; 140 UART1->BRR2 |= (u8)((u8)(((BaudRate_Mantissa100 - (BaudRate_Mantissa * 100)) << 4) / 100) & (u8)0x0F); /**< Set the fraction of UART1DIV */
514 00bc 96 ldw x,sp
515 00bd 1c0009 addw x,#OFST-3
516 00c0 cd0000 call c_ltor
518 00c3 a664 ld a,#100
519 00c5 cd0000 call c_smul
521 00c8 96 ldw x,sp
522 00c9 1c0001 addw x,#OFST-11
523 00cc cd0000 call c_rtol
525 00cf 96 ldw x,sp
526 00d0 1c0005 addw x,#OFST-7
527 00d3 cd0000 call c_ltor
529 00d6 96 ldw x,sp
530 00d7 1c0001 addw x,#OFST-11
531 00da cd0000 call c_lsub
533 00dd a604 ld a,#4
534 00df cd0000 call c_llsh
536 00e2 ae0000 ldw x,#L01
537 00e5 cd0000 call c_ludv
539 00e8 b603 ld a,c_lreg+3
540 00ea a40f and a,#15
541 00ec ca5233 or a,21043
542 00ef c75233 ld 21043,a
543 ; 141 UART1->BRR2 |= (u8)((BaudRate_Mantissa >> 4) & (u8)0xF0); /**< Set the MSB mantissa of UART1DIV */
545 00f2 96 ldw x,sp
546 00f3 1c0009 addw x,#OFST-3
547 00f6 cd0000 call c_ltor
549 00f9 a604 ld a,#4
550 00fb cd0000 call c_lursh
552 00fe b603 ld a,c_lreg+3
553 0100 a4f0 and a,#240
554 0102 b703 ld c_lreg+3,a
555 0104 3f02 clr c_lreg+2
556 0106 3f01 clr c_lreg+1
557 0108 3f00 clr c_lreg
558 010a b603 ld a,c_lreg+3
559 010c ca5233 or a,21043
560 010f c75233 ld 21043,a
561 ; 142 UART1->BRR1 |= (u8)BaudRate_Mantissa; /**< Set the LSB mantissa of UART1DIV */
563 0112 c65232 ld a,21042
564 0115 1a0c or a,(OFST+0,sp)
565 0117 c75232 ld 21042,a
566 ; 144 UART1->CR2 &= (u8)~(UART1_CR2_TEN | UART1_CR2_REN); /**< Disable the Transmitter and Receiver before seting the LBCL, CPOL and CPHA bits */
568 011a c65235 ld a,21045
569 011d a4f3 and a,#243
570 011f c75235 ld 21045,a
571 ; 145 UART1->CR3 &= (u8)~(UART1_CR3_CPOL | UART1_CR3_CPHA | UART1_CR3_LBCL); /**< Clear the Clock Polarity, lock Phase, Last Bit Clock pulse */
573 0122 c65236 ld a,21046
574 0125 a4f8 and a,#248
575 0127 c75236 ld 21046,a
576 ; 146 UART1->CR3 |= (u8)((u8)SyncMode & (u8)(UART1_CR3_CPOL | UART1_CR3_CPHA | UART1_CR3_LBCL)); /**< Set the Clock Polarity, lock Phase, Last Bit Clock pulse */
578 012a 7b16 ld a,(OFST+10,sp)
579 012c a407 and a,#7
580 012e ca5236 or a,21046
581 0131 c75236 ld 21046,a
582 ; 148 if ((u8)Mode & (u8)UART1_MODE_TX_ENABLE)
584 0134 7b17 ld a,(OFST+11,sp)
585 0136 a504 bcp a,#4
586 0138 2706 jreq L171
587 ; 150 UART1->CR2 |= (u8)UART1_CR2_TEN; /**< Set the Transmitter Enable bit */
589 013a 72165235 bset 21045,#3
591 013e 2004 jra L371
592 0140 L171:
593 ; 154 UART1->CR2 &= (u8)(~UART1_CR2_TEN); /**< Clear the Transmitter Disable bit */
595 0140 72175235 bres 21045,#3
596 0144 L371:
597 ; 156 if ((u8)Mode & (u8)UART1_MODE_RX_ENABLE)
599 0144 7b17 ld a,(OFST+11,sp)
600 0146 a508 bcp a,#8
601 0148 2706 jreq L571
602 ; 158 UART1->CR2 |= (u8)UART1_CR2_REN; /**< Set the Receiver Enable bit */
604 014a 72145235 bset 21045,#2
606 014e 2004 jra L771
607 0150 L571:
608 ; 162 UART1->CR2 &= (u8)(~UART1_CR2_REN); /**< Clear the Receiver Disable bit */
610 0150 72155235 bres 21045,#2
611 0154 L771:
612 ; 165 if ((u8)SyncMode&(u8)UART1_SYNCMODE_CLOCK_DISABLE)
614 0154 7b16 ld a,(OFST+10,sp)
615 0156 a580 bcp a,#128
616 0158 2706 jreq L102
617 ; 167 UART1->CR3 &= (u8)(~UART1_CR3_CKEN); /**< Clear the Clock Enable bit */
619 015a 72175236 bres 21046,#3
621 015e 200a jra L302
622 0160 L102:
623 ; 172 UART1->CR3 |= (u8)((u8)SyncMode & UART1_CR3_CKEN);
625 0160 7b16 ld a,(OFST+10,sp)
626 0162 a408 and a,#8
627 0164 ca5236 or a,21046
628 0167 c75236 ld 21046,a
629 016a L302:
630 ; 174 }
633 016a 5b0c addw sp,#12
634 016c 81 ret
689 ; 195 void UART1_Cmd(FunctionalState NewState)
689 ; 196 {
690 switch .text
691 016d _UART1_Cmd:
695 ; 197 if (NewState != DISABLE)
697 016d 4d tnz a
698 016e 2706 jreq L332
699 ; 199 UART1->CR1 &= (u8)(~UART1_CR1_UARTD); /**< UART1 Enable */
701 0170 721b5234 bres 21044,#5
703 0174 2004 jra L532
704 0176 L332:
705 ; 203 UART1->CR1 |= UART1_CR1_UARTD; /**< UART1 Disable (for low power consumption) */
707 0176 721a5234 bset 21044,#5
708 017a L532:
709 ; 205 }
712 017a 81 ret
833 ; 231 void UART1_ITConfig(UART1_IT_TypeDef UART1_IT, FunctionalState NewState)
833 ; 232 {
834 switch .text
835 017b _UART1_ITConfig:
837 017b 89 pushw x
838 017c 89 pushw x
839 00000002 OFST: set 2
842 ; 233 u8 uartreg, itpos = 0x00;
844 ; 234 assert_param(IS_UART1_CONFIG_IT_OK(UART1_IT));
846 ; 235 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
848 ; 238 uartreg = (u8)(UART1_IT >> (u8)0x08);
850 017d 9e ld a,xh
851 017e 6b01 ld (OFST-1,sp),a
852 ; 240 itpos = (u8)((u8)1 << (u8)((u8)UART1_IT & (u8)0x0F));
854 0180 9f ld a,xl
855 0181 a40f and a,#15
856 0183 5f clrw x
857 0184 97 ld xl,a
858 0185 a601 ld a,#1
859 0187 5d tnzw x
860 0188 2704 jreq L61
861 018a L02:
862 018a 48 sll a
863 018b 5a decw x
864 018c 26fc jrne L02
865 018e L61:
866 018e 6b02 ld (OFST+0,sp),a
867 ; 242 if (NewState != DISABLE)
869 0190 0d07 tnz (OFST+5,sp)
870 0192 272a jreq L113
871 ; 245 if (uartreg == 0x01)
873 0194 7b01 ld a,(OFST-1,sp)
874 0196 a101 cp a,#1
875 0198 260a jrne L313
876 ; 247 UART1->CR1 |= itpos;
878 019a c65234 ld a,21044
879 019d 1a02 or a,(OFST+0,sp)
880 019f c75234 ld 21044,a
882 01a2 2045 jra L323
883 01a4 L313:
884 ; 249 else if (uartreg == 0x02)
886 01a4 7b01 ld a,(OFST-1,sp)
887 01a6 a102 cp a,#2
888 01a8 260a jrne L713
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -