📄 stm8s_tim3.ls
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3023 032c 81 ret
3058 ; 1259 void TIM3_ClearFlag(TIM3_FLAG_TypeDef TIM3_FLAG)
3058 ; 1260 {
3059 switch .text
3060 032d _TIM3_ClearFlag:
3062 032d 89 pushw x
3063 00000000 OFST: set 0
3066 ; 1262 assert_param(IS_TIM3_CLEAR_FLAG_OK(TIM3_FLAG));
3068 ; 1265 TIM3->SR1 = (u8)(~((u8)(TIM3_FLAG)));
3070 032e 9f ld a,xl
3071 032f 43 cpl a
3072 0330 c75322 ld 21282,a
3073 ; 1266 TIM3->SR2 = (u8)(~((u8)(TIM3_FLAG >> 8)));
3075 0333 7b01 ld a,(OFST+1,sp)
3076 0335 43 cpl a
3077 0336 c75323 ld 21283,a
3078 ; 1267 }
3081 0339 85 popw x
3082 033a 81 ret
3142 ; 1290 ITStatus TIM3_GetITStatus(TIM3_IT_TypeDef TIM3_IT)
3142 ; 1291 {
3143 switch .text
3144 033b _TIM3_GetITStatus:
3146 033b 88 push a
3147 033c 89 pushw x
3148 00000002 OFST: set 2
3151 ; 1292 ITStatus bitstatus = RESET;
3153 ; 1294 u8 TIM3_itStatus = 0x0, TIM3_itEnable = 0x0;
3157 ; 1297 assert_param(IS_TIM3_GET_IT_OK(TIM3_IT));
3159 ; 1299 TIM3_itStatus = (u8)(TIM3->SR1 & TIM3_IT);
3161 033d c45322 and a,21282
3162 0340 6b01 ld (OFST-1,sp),a
3163 ; 1301 TIM3_itEnable = (u8)(TIM3->IER & TIM3_IT);
3165 0342 c65321 ld a,21281
3166 0345 1403 and a,(OFST+1,sp)
3167 0347 6b02 ld (OFST+0,sp),a
3168 ; 1303 if ((TIM3_itStatus != (u8)RESET ) && (TIM3_itEnable != (u8)RESET ))
3170 0349 0d01 tnz (OFST-1,sp)
3171 034b 270a jreq L7741
3173 034d 0d02 tnz (OFST+0,sp)
3174 034f 2706 jreq L7741
3175 ; 1305 bitstatus = SET;
3177 0351 a601 ld a,#1
3178 0353 6b02 ld (OFST+0,sp),a
3180 0355 2002 jra L1051
3181 0357 L7741:
3182 ; 1309 bitstatus = RESET;
3184 0357 0f02 clr (OFST+0,sp)
3185 0359 L1051:
3186 ; 1311 return (ITStatus)(bitstatus);
3188 0359 7b02 ld a,(OFST+0,sp)
3191 035b 5b03 addw sp,#3
3192 035d 81 ret
3228 ; 1333 void TIM3_ClearITPendingBit(TIM3_IT_TypeDef TIM3_IT)
3228 ; 1334 {
3229 switch .text
3230 035e _TIM3_ClearITPendingBit:
3234 ; 1336 assert_param(IS_TIM3_IT_OK(TIM3_IT));
3236 ; 1339 TIM3->SR1 = (u8)(~TIM3_IT);
3238 035e 43 cpl a
3239 035f c75322 ld 21282,a
3240 ; 1340 }
3243 0362 81 ret
3289 ; 1368 static void TI1_Config(u8 TIM3_ICPolarity,
3289 ; 1369 u8 TIM3_ICSelection,
3289 ; 1370 u8 TIM3_ICFilter)
3289 ; 1371 {
3290 switch .text
3291 0363 L3_TI1_Config:
3293 0363 89 pushw x
3294 0364 88 push a
3295 00000001 OFST: set 1
3298 ; 1373 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC1E);
3300 0365 72115327 bres 21287,#0
3301 ; 1376 TIM3->CCMR1 = (u8)((TIM3->CCMR1 & (u8)(~( TIM3_CCMR_CCxS | TIM3_CCMR_ICxF ))) | (u8)(( (TIM3_ICSelection)) | ((u8)( TIM3_ICFilter << 4))));
3303 0369 7b06 ld a,(OFST+5,sp)
3304 036b 97 ld xl,a
3305 036c a610 ld a,#16
3306 036e 42 mul x,a
3307 036f 9f ld a,xl
3308 0370 1a03 or a,(OFST+2,sp)
3309 0372 6b01 ld (OFST+0,sp),a
3310 0374 c65325 ld a,21285
3311 0377 a40c and a,#12
3312 0379 1a01 or a,(OFST+0,sp)
3313 037b c75325 ld 21285,a
3314 ; 1379 if (TIM3_ICPolarity != TIM3_ICPOLARITY_RISING)
3316 037e 0d02 tnz (OFST+1,sp)
3317 0380 2706 jreq L1451
3318 ; 1381 TIM3->CCER1 |= TIM3_CCER1_CC1P;
3320 0382 72125327 bset 21287,#1
3322 0386 2004 jra L3451
3323 0388 L1451:
3324 ; 1385 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC1P);
3326 0388 72135327 bres 21287,#1
3327 038c L3451:
3328 ; 1388 TIM3->CCER1 |= TIM3_CCER1_CC1E;
3330 038c 72105327 bset 21287,#0
3331 ; 1389 }
3334 0390 5b03 addw sp,#3
3335 0392 81 ret
3381 ; 1417 static void TI2_Config(u8 TIM3_ICPolarity,
3381 ; 1418 u8 TIM3_ICSelection,
3381 ; 1419 u8 TIM3_ICFilter)
3381 ; 1420 {
3382 switch .text
3383 0393 L5_TI2_Config:
3385 0393 89 pushw x
3386 0394 88 push a
3387 00000001 OFST: set 1
3390 ; 1422 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC2E);
3392 0395 72195327 bres 21287,#4
3393 ; 1425 TIM3->CCMR2 = (u8)((TIM3->CCMR2 & (u8)(~( TIM3_CCMR_CCxS | TIM3_CCMR_ICxF ))) | (u8)(( (TIM3_ICSelection)) | ((u8)( TIM3_ICFilter << 4))));
3395 0399 7b06 ld a,(OFST+5,sp)
3396 039b 97 ld xl,a
3397 039c a610 ld a,#16
3398 039e 42 mul x,a
3399 039f 9f ld a,xl
3400 03a0 1a03 or a,(OFST+2,sp)
3401 03a2 6b01 ld (OFST+0,sp),a
3402 03a4 c65326 ld a,21286
3403 03a7 a40c and a,#12
3404 03a9 1a01 or a,(OFST+0,sp)
3405 03ab c75326 ld 21286,a
3406 ; 1429 if (TIM3_ICPolarity != TIM3_ICPOLARITY_RISING)
3408 03ae 0d02 tnz (OFST+1,sp)
3409 03b0 2706 jreq L5651
3410 ; 1431 TIM3->CCER1 |= TIM3_CCER1_CC2P;
3412 03b2 721a5327 bset 21287,#5
3414 03b6 2004 jra L7651
3415 03b8 L5651:
3416 ; 1435 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC2P);
3418 03b8 721b5327 bres 21287,#5
3419 03bc L7651:
3420 ; 1439 TIM3->CCER1 |= TIM3_CCER1_CC2E;
3422 03bc 72185327 bset 21287,#4
3423 ; 1441 }
3426 03c0 5b03 addw sp,#3
3427 03c2 81 ret
3486 ; 1461 u32 TIM3_ComputeLsiClockFreq(u32 TimerClockFreq)
3486 ; 1462 {
3487 switch .text
3488 03c3 _TIM3_ComputeLsiClockFreq:
3490 03c3 520c subw sp,#12
3491 0000000c OFST: set 12
3494 ; 1467 TIM3_ICInit(TIM3_CHANNEL_1, TIM3_ICPOLARITY_RISING, TIM3_ICSELECTION_DIRECTTI, TIM3_ICPSC_DIV8, 0);
3496 03c5 4b00 push #0
3497 03c7 4b0c push #12
3498 03c9 4b01 push #1
3499 03cb 5f clrw x
3500 03cc 4f clr a
3501 03cd 95 ld xh,a
3502 03ce cd00b9 call _TIM3_ICInit
3504 03d1 5b03 addw sp,#3
3505 ; 1471 TIM3_ITConfig(TIM3_IT_CC1, ENABLE);
3507 03d3 ae0001 ldw x,#1
3508 03d6 a602 ld a,#2
3509 03d8 95 ld xh,a
3510 03d9 cd0167 call _TIM3_ITConfig
3512 ; 1474 TIM3_Cmd(ENABLE);
3514 03dc a601 ld a,#1
3515 03de cd0159 call _TIM3_Cmd
3517 ; 1476 TIM3->SR1 = 0x00;
3519 03e1 725f5322 clr 21282
3520 ; 1477 TIM3->SR2 = 0x00;
3522 03e5 725f5323 clr 21283
3523 ; 1480 TIM3_ClearFlag(TIM3_FLAG_CC1);
3525 03e9 ae0002 ldw x,#2
3526 03ec cd032d call _TIM3_ClearFlag
3529 03ef L5161:
3530 ; 1483 while ((TIM3->SR1 & TIM3_FLAG_CC1) != TIM3_FLAG_CC1);
3532 03ef c65322 ld a,21282
3533 03f2 a402 and a,#2
3534 03f4 a102 cp a,#2
3535 03f6 26f7 jrne L5161
3536 ; 1485 ICValue1 = TIM3_GetCapture1();
3538 03f8 cd029f call _TIM3_GetCapture1
3540 03fb 1f09 ldw (OFST-3,sp),x
3541 ; 1486 TIM3_ClearFlag(TIM3_FLAG_CC1);
3543 03fd ae0002 ldw x,#2
3544 0400 cd032d call _TIM3_ClearFlag
3547 0403 L3261:
3548 ; 1489 while ((TIM3->SR1 & TIM3_FLAG_CC1) != TIM3_FLAG_CC1);
3550 0403 c65322 ld a,21282
3551 0406 a402 and a,#2
3552 0408 a102 cp a,#2
3553 040a 26f7 jrne L3261
3554 ; 1491 ICValue2 = TIM3_GetCapture1();
3556 040c cd029f call _TIM3_GetCapture1
3558 040f 1f0b ldw (OFST-1,sp),x
3559 ; 1492 TIM3_ClearFlag(TIM3_FLAG_CC1);
3561 0411 ae0002 ldw x,#2
3562 0414 cd032d call _TIM3_ClearFlag
3564 ; 1495 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC1E);
3566 0417 72115327 bres 21287,#0
3567 ; 1497 TIM3->CCMR1 = 0x00;
3569 041b 725f5325 clr 21285
3570 ; 1499 TIM3_Cmd(DISABLE);
3572 041f 4f clr a
3573 0420 cd0159 call _TIM3_Cmd
3575 ; 1502 LSIClockFreq = (8 * TimerClockFreq) / (ICValue2 - ICValue1);
3577 0423 1e0b ldw x,(OFST-1,sp)
3578 0425 72f009 subw x,(OFST-3,sp)
3579 0428 cd0000 call c_uitolx
3581 042b 96 ldw x,sp
3582 042c 1c0001 addw x,#OFST-11
3583 042f cd0000 call c_rtol
3585 0432 96 ldw x,sp
3586 0433 1c000f addw x,#OFST+3
3587 0436 cd0000 call c_ltor
3589 0439 a603 ld a,#3
3590 043b cd0000 call c_llsh
3592 043e 96 ldw x,sp
3593 043f 1c0001 addw x,#OFST-11
3594 0442 cd0000 call c_ludv
3596 0445 96 ldw x,sp
3597 0446 1c0005 addw x,#OFST-7
3598 0449 cd0000 call c_rtol
3600 ; 1503 return (u32)LSIClockFreq;
3602 044c 96 ldw x,sp
3603 044d 1c0005 addw x,#OFST-7
3604 0450 cd0000 call c_ltor
3608 0453 5b0c addw sp,#12
3609 0455 81 ret
3622 xdef _TIM3_ComputeLsiClockFreq
3623 xdef _TIM3_ClearITPendingBit
3624 xdef _TIM3_GetITStatus
3625 xdef _TIM3_ClearFlag
3626 xdef _TIM3_GetFlagStatus
3627 xdef _TIM3_GetPrescaler
3628 xdef _TIM3_GetCounter
3629 xdef _TIM3_GetCapture2
3630 xdef _TIM3_GetCapture1
3631 xdef _TIM3_SetIC2Prescaler
3632 xdef _TIM3_SetIC1Prescaler
3633 xdef _TIM3_SetCompare2
3634 xdef _TIM3_SetCompare1
3635 xdef _TIM3_SetAutoreload
3636 xdef _TIM3_SetCounter
3637 xdef _TIM3_SelectOCxM
3638 xdef _TIM3_CCxCmd
3639 xdef _TIM3_OC2PolarityConfig
3640 xdef _TIM3_OC1PolarityConfig
3641 xdef _TIM3_GenerateEvent
3642 xdef _TIM3_OC2PreloadConfig
3643 xdef _TIM3_OC1PreloadConfig
3644 xdef _TIM3_ARRPreloadConfig
3645 xdef _TIM3_ForcedOC2Config
3646 xdef _TIM3_ForcedOC1Config
3647 xdef _TIM3_PrescalerConfig
3648 xdef _TIM3_SelectOnePulseMode
3649 xdef _TIM3_UpdateRequestConfig
3650 xdef _TIM3_UpdateDisableConfig
3651 xdef _TIM3_ITConfig
3652 xdef _TIM3_Cmd
3653 xdef _TIM3_PWMIConfig
3654 xdef _TIM3_ICInit
3655 xdef _TIM3_OC2Init
3656 xdef _TIM3_OC1Init
3657 xdef _TIM3_TimeBaseInit
3658 xdef _TIM3_DeInit
3659 xref.b c_x
3678 xref c_ludv
3679 xref c_rtol
3680 xref c_uitolx
3681 xref c_llsh
3682 xref c_ltor
3683 end
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