📄 stm8s_tim3.ls
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1038 0134 88 push a
1039 0135 7b08 ld a,(OFST+6,sp)
1040 0137 97 ld xl,a
1041 0138 7b05 ld a,(OFST+3,sp)
1042 013a 95 ld xh,a
1043 013b cd0393 call L5_TI2_Config
1045 013e 84 pop a
1046 ; 353 TIM3_SetIC2Prescaler(TIM3_ICPrescaler);
1048 013f 7b08 ld a,(OFST+6,sp)
1049 0141 cd0292 call _TIM3_SetIC2Prescaler
1051 ; 356 TI1_Config(icpolarity, icselection, TIM3_ICFilter);
1053 0144 7b09 ld a,(OFST+7,sp)
1054 0146 88 push a
1055 0147 7b03 ld a,(OFST+1,sp)
1056 0149 97 ld xl,a
1057 014a 7b02 ld a,(OFST+0,sp)
1058 014c 95 ld xh,a
1059 014d cd0363 call L3_TI1_Config
1061 0150 84 pop a
1062 ; 359 TIM3_SetIC1Prescaler(TIM3_ICPrescaler);
1064 0151 7b08 ld a,(OFST+6,sp)
1065 0153 cd0285 call _TIM3_SetIC1Prescaler
1067 0156 L114:
1068 ; 361 }
1071 0156 5b04 addw sp,#4
1072 0158 81 ret
1127 ; 379 void TIM3_Cmd(FunctionalState NewState)
1127 ; 380 {
1128 switch .text
1129 0159 _TIM3_Cmd:
1133 ; 382 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1135 ; 385 if (NewState != DISABLE)
1137 0159 4d tnz a
1138 015a 2706 jreq L144
1139 ; 387 TIM3->CR1 |= TIM3_CR1_CEN;
1141 015c 72105320 bset 21280,#0
1143 0160 2004 jra L344
1144 0162 L144:
1145 ; 391 TIM3->CR1 &= (u8)(~TIM3_CR1_CEN);
1147 0162 72115320 bres 21280,#0
1148 0166 L344:
1149 ; 393 }
1152 0166 81 ret
1224 ; 417 void TIM3_ITConfig(TIM3_IT_TypeDef TIM3_IT, FunctionalState NewState)
1224 ; 418 {
1225 switch .text
1226 0167 _TIM3_ITConfig:
1228 0167 89 pushw x
1229 00000000 OFST: set 0
1232 ; 420 assert_param(IS_TIM3_IT_OK(TIM3_IT));
1234 ; 421 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1236 ; 423 if (NewState != DISABLE)
1238 0168 9f ld a,xl
1239 0169 4d tnz a
1240 016a 2709 jreq L105
1241 ; 426 TIM3->IER |= TIM3_IT;
1243 016c 9e ld a,xh
1244 016d ca5321 or a,21281
1245 0170 c75321 ld 21281,a
1247 0173 2009 jra L305
1248 0175 L105:
1249 ; 431 TIM3->IER &= (u8)(~TIM3_IT);
1251 0175 7b01 ld a,(OFST+1,sp)
1252 0177 43 cpl a
1253 0178 c45321 and a,21281
1254 017b c75321 ld 21281,a
1255 017e L305:
1256 ; 433 }
1259 017e 85 popw x
1260 017f 81 ret
1296 ; 451 void TIM3_UpdateDisableConfig(FunctionalState NewState)
1296 ; 452 {
1297 switch .text
1298 0180 _TIM3_UpdateDisableConfig:
1302 ; 454 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1304 ; 457 if (NewState != DISABLE)
1306 0180 4d tnz a
1307 0181 2706 jreq L325
1308 ; 459 TIM3->CR1 |= TIM3_CR1_UDIS;
1310 0183 72125320 bset 21280,#1
1312 0187 2004 jra L525
1313 0189 L325:
1314 ; 463 TIM3->CR1 &= (u8)(~TIM3_CR1_UDIS);
1316 0189 72135320 bres 21280,#1
1317 018d L525:
1318 ; 465 }
1321 018d 81 ret
1379 ; 484 void TIM3_UpdateRequestConfig(TIM3_UpdateSource_TypeDef TIM3_UpdateSource)
1379 ; 485 {
1380 switch .text
1381 018e _TIM3_UpdateRequestConfig:
1385 ; 487 assert_param(IS_TIM3_UPDATE_SOURCE_OK(TIM3_UpdateSource));
1387 ; 490 if (TIM3_UpdateSource != TIM3_UPDATESOURCE_GLOBAL)
1389 018e 4d tnz a
1390 018f 2706 jreq L555
1391 ; 492 TIM3->CR1 |= TIM3_CR1_URS;
1393 0191 72145320 bset 21280,#2
1395 0195 2004 jra L755
1396 0197 L555:
1397 ; 496 TIM3->CR1 &= (u8)(~TIM3_CR1_URS);
1399 0197 72155320 bres 21280,#2
1400 019b L755:
1401 ; 498 }
1404 019b 81 ret
1461 ; 518 void TIM3_SelectOnePulseMode(TIM3_OPMode_TypeDef TIM3_OPMode)
1461 ; 519 {
1462 switch .text
1463 019c _TIM3_SelectOnePulseMode:
1467 ; 521 assert_param(IS_TIM3_OPM_MODE_OK(TIM3_OPMode));
1469 ; 524 if (TIM3_OPMode != TIM3_OPMODE_REPETITIVE)
1471 019c 4d tnz a
1472 019d 2706 jreq L706
1473 ; 526 TIM3->CR1 |= TIM3_CR1_OPM;
1475 019f 72165320 bset 21280,#3
1477 01a3 2004 jra L116
1478 01a5 L706:
1479 ; 530 TIM3->CR1 &= (u8)(~TIM3_CR1_OPM);
1481 01a5 72175320 bres 21280,#3
1482 01a9 L116:
1483 ; 533 }
1486 01a9 81 ret
1554 ; 573 void TIM3_PrescalerConfig(TIM3_Prescaler_TypeDef Prescaler,
1554 ; 574 TIM3_PSCReloadMode_TypeDef TIM3_PSCReloadMode)
1554 ; 575 {
1555 switch .text
1556 01aa _TIM3_PrescalerConfig:
1560 ; 577 assert_param(IS_TIM3_PRESCALER_RELOAD_OK(TIM3_PSCReloadMode));
1562 ; 578 assert_param(IS_TIM3_PRESCALER_OK(Prescaler));
1564 ; 581 TIM3->PSCR = Prescaler;
1566 01aa 9e ld a,xh
1567 01ab c7532a ld 21290,a
1568 ; 584 TIM3->EGR = TIM3_PSCReloadMode;
1570 01ae 9f ld a,xl
1571 01af c75324 ld 21284,a
1572 ; 585 }
1575 01b2 81 ret
1633 ; 605 void TIM3_ForcedOC1Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
1633 ; 606 {
1634 switch .text
1635 01b3 _TIM3_ForcedOC1Config:
1637 01b3 88 push a
1638 00000000 OFST: set 0
1641 ; 608 assert_param(IS_TIM3_FORCED_ACTION_OK(TIM3_ForcedAction));
1643 ; 611 TIM3->CCMR1 = (u8)((TIM3->CCMR1 & (u8)(~TIM3_CCMR_OCM)) | (u8)TIM3_ForcedAction);
1645 01b4 c65325 ld a,21285
1646 01b7 a48f and a,#143
1647 01b9 1a01 or a,(OFST+1,sp)
1648 01bb c75325 ld 21285,a
1649 ; 612 }
1652 01be 84 pop a
1653 01bf 81 ret
1689 ; 632 void TIM3_ForcedOC2Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
1689 ; 633 {
1690 switch .text
1691 01c0 _TIM3_ForcedOC2Config:
1693 01c0 88 push a
1694 00000000 OFST: set 0
1697 ; 635 assert_param(IS_TIM3_FORCED_ACTION_OK(TIM3_ForcedAction));
1699 ; 638 TIM3->CCMR2 = (u8)((TIM3->CCMR2 & (u8)(~TIM3_CCMR_OCM)) | (u8)TIM3_ForcedAction);
1701 01c1 c65326 ld a,21286
1702 01c4 a48f and a,#143
1703 01c6 1a01 or a,(OFST+1,sp)
1704 01c8 c75326 ld 21286,a
1705 ; 639 }
1708 01cb 84 pop a
1709 01cc 81 ret
1745 ; 657 void TIM3_ARRPreloadConfig(FunctionalState NewState)
1745 ; 658 {
1746 switch .text
1747 01cd _TIM3_ARRPreloadConfig:
1751 ; 660 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1753 ; 663 if (NewState != DISABLE)
1755 01cd 4d tnz a
1756 01ce 2706 jreq L727
1757 ; 665 TIM3->CR1 |= TIM3_CR1_ARPE;
1759 01d0 721e5320 bset 21280,#7
1761 01d4 2004 jra L137
1762 01d6 L727:
1763 ; 669 TIM3->CR1 &= (u8)(~TIM3_CR1_ARPE);
1765 01d6 721f5320 bres 21280,#7
1766 01da L137:
1767 ; 671 }
1770 01da 81 ret
1806 ; 689 void TIM3_OC1PreloadConfig(FunctionalState NewState)
1806 ; 690 {
1807 switch .text
1808 01db _TIM3_OC1PreloadConfig:
1812 ; 692 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1814 ; 695 if (NewState != DISABLE)
1816 01db 4d tnz a
1817 01dc 2706 jreq L157
1818 ; 697 TIM3->CCMR1 |= TIM3_CCMR_OCxPE;
1820 01de 72165325 bset 21285,#3
1822 01e2 2004 jra L357
1823 01e4 L157:
1824 ; 701 TIM3->CCMR1 &= (u8)(~TIM3_CCMR_OCxPE);
1826 01e4 72175325 bres 21285,#3
1827 01e8 L357:
1828 ; 703 }
1831 01e8 81 ret
1867 ; 721 void TIM3_OC2PreloadConfig(FunctionalState NewState)
1867 ; 722 {
1868 switch .text
1869 01e9 _TIM3_OC2PreloadConfig:
1873 ; 724 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1875 ; 727 if (NewState != DISABLE)
1877 01e9 4d tnz a
1878 01ea 2706 jreq L377
1879 ; 729 TIM3->CCMR2 |= TIM3_CCMR_OCxPE;
1881 01ec 72165326 bset 21286,#3
1883 01f0 2004 jra L577
1884 01f2 L377:
1885 ; 733 TIM3->CCMR2 &= (u8)(~TIM3_CCMR_OCxPE);
1887 01f2 72175326 bres 21286,#3
1888 01f6 L577:
1889 ; 735 }
1892 01f6 81 ret
1957 ; 755 void TIM3_GenerateEvent(TIM3_EventSource_TypeDef TIM3_EventSource)
1957 ; 756 {
1958 switch .text
1959 01f7 _TIM3_GenerateEvent:
1963 ; 758 assert_param(IS_TIM3_EVENT_SOURCE_OK(TIM3_EventSource));
1965 ; 761 TIM3->EGR = TIM3_EventSource;
1967 01f7 c75324 ld 21284,a
1968 ; 762 }
1971 01fa 81 ret
2007 ; 782 void TIM3_OC1PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
2007 ; 783 {
2008 switch .text
2009 01fb _TIM3_OC1PolarityConfig:
2013 ; 785 assert_param(IS_TIM3_OC_POLARITY_OK(TIM3_OCPolarity));
2015 ; 788 if (TIM3_OCPolarity != TIM3_OCPOLARITY_HIGH)
2017 01fb 4d tnz a
2018 01fc 2706 jreq L5401
2019 ; 790 TIM3->CCER1 |= TIM3_CCER1_CC1P;
2021 01fe 72125327 bset 21287,#1
2023 0202 2004 jra L7401
2024 0204 L5401:
2025 ; 794 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC1P);
2027 0204 72135327 bres 21287,#1
2028 0208 L7401:
2029 ; 796 }
2032 0208 81 ret
2068 ; 816 void TIM3_OC2PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
2068 ; 817 {
2069 switch .text
2070 0209 _TIM3_OC2PolarityConfig:
2074 ; 819 assert_param(IS_TIM3_OC_POLARITY_OK(TIM3_OCPolarity));
2076 ; 822 if (TIM3_OCPolarity != TIM3_OCPOLARITY_HIGH)
2078 0209 4d tnz a
2079 020a 2706 jreq L7601
2080 ; 824 TIM3->CCER1 |= TIM3_CCER1_CC2P;
2082 020c 721a5327 bset 21287,#5
2084 0210 2004 jra L1701
2085 0212 L7601:
2086 ; 828 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC2P);
2088 0212 721b5327 bres 21287,#5
2089 0216 L1701:
2090 ; 830 }
2093 0216 81 ret
2138 ; 852 void TIM3_CCxCmd(TIM3_Channel_TypeDef TIM3_Channel, FunctionalState NewState)
2138 ; 853 {
2139 switch .text
2140 0217 _TIM3_CCxCmd:
2142 0217 89 pushw x
2143 00000000 OFST: set 0
2146 ; 855 assert_param(IS_TIM3_CHANNEL_OK(TIM3_Channel));
2148 ; 856 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2150 ; 858 if (TIM3_Channel == TIM3_CHANNEL_1)
2152 0218 9e ld a,xh
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