📄 stm8s_spi.ls
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1007 00b1 2707 jreq L144
1008 ; 335 crcreg = SPI->TXCRCR; /* Get the Tx CRC register*/
1010 00b3 c65207 ld a,20999
1011 00b6 6b01 ld (OFST+0,sp),a
1013 00b8 2005 jra L344
1014 00ba L144:
1015 ; 339 crcreg = SPI->RXCRCR; /* Get the Rx CRC register*/
1017 00ba c65206 ld a,20998
1018 00bd 6b01 ld (OFST+0,sp),a
1019 00bf L344:
1020 ; 343 return crcreg;
1022 00bf 7b01 ld a,(OFST+0,sp)
1025 00c1 5b01 addw sp,#1
1026 00c3 81 ret
1051 ; 359 void SPI_ResetCRC(void)
1051 ; 360 {
1052 switch .text
1053 00c4 _SPI_ResetCRC:
1057 ; 363 SPI_CalculateCRCCmd(ENABLE);
1059 00c4 a601 ld a,#1
1060 00c6 add3 call _SPI_CalculateCRCCmd
1062 ; 366 SPI_Cmd(ENABLE);
1064 00c8 a601 ld a,#1
1065 00ca cd0046 call _SPI_Cmd
1067 ; 367 }
1070 00cd 81 ret
1094 ; 384 u8 SPI_GetCRCPolynomial(void)
1094 ; 385 {
1095 switch .text
1096 00ce _SPI_GetCRCPolynomial:
1100 ; 386 return SPI->CRCPR; /* Return the CRC polynomial register */
1102 00ce c65205 ld a,20997
1105 00d1 81 ret
1161 ; 402 void SPI_BiDirectionalLineConfig(SPI_Direction_TypeDef SPI_Direction)
1161 ; 403 {
1162 switch .text
1163 00d2 _SPI_BiDirectionalLineConfig:
1167 ; 405 assert_param(IS_SPI_DIRECTION_OK(SPI_Direction));
1169 ; 407 if (SPI_Direction != SPI_DIRECTION_RX)
1171 00d2 4d tnz a
1172 00d3 2706 jreq L315
1173 ; 409 SPI->CR2 |= SPI_CR2_BDOE; /* Set the Tx only mode*/
1175 00d5 721c5201 bset 20993,#6
1177 00d9 2004 jra L515
1178 00db L315:
1179 ; 413 SPI->CR2 &= (u8)(~SPI_CR2_BDOE); /* Set the Rx only mode*/
1181 00db 721d5201 bres 20993,#6
1182 00df L515:
1183 ; 415 }
1186 00df 81 ret
1307 ; 435 FlagStatus SPI_GetFlagStatus(SPI_Flag_TypeDef SPI_FLAG)
1307 ; 436 {
1308 switch .text
1309 00e0 _SPI_GetFlagStatus:
1311 00e0 88 push a
1312 00000001 OFST: set 1
1315 ; 437 FlagStatus status = RESET;
1317 ; 439 assert_param(IS_SPI_FLAGS_OK(SPI_FLAG));
1319 ; 442 if ((SPI->SR & (u8)SPI_FLAG) != (u8)RESET)
1321 00e1 c45203 and a,20995
1322 00e4 2706 jreq L375
1323 ; 444 status = SET; /* SPI_FLAG is set */
1325 00e6 a601 ld a,#1
1326 00e8 6b01 ld (OFST+0,sp),a
1328 00ea 2002 jra L575
1329 00ec L375:
1330 ; 448 status = RESET; /* SPI_FLAG is reset*/
1332 00ec 0f01 clr (OFST+0,sp)
1333 00ee L575:
1334 ; 452 return status;
1336 00ee 7b01 ld a,(OFST+0,sp)
1339 00f0 5b01 addw sp,#1
1340 00f2 81 ret
1375 ; 479 void SPI_ClearFlag(SPI_Flag_TypeDef SPI_FLAG)
1375 ; 480 {
1376 switch .text
1377 00f3 _SPI_ClearFlag:
1381 ; 481 assert_param(IS_SPI_CLEAR_FLAGS_OK(SPI_FLAG));
1383 ; 483 SPI->SR = (u8)(~SPI_FLAG);
1385 00f3 43 cpl a
1386 00f4 c75203 ld 20995,a
1387 ; 484 }
1390 00f7 81 ret
1464 ; 509 ITStatus SPI_GetITStatus(SPI_IT_TypeDef SPI_IT)
1464 ; 510 {
1465 switch .text
1466 00f8 _SPI_GetITStatus:
1468 00f8 88 push a
1469 00f9 89 pushw x
1470 00000002 OFST: set 2
1473 ; 511 ITStatus pendingbitstatus = RESET;
1475 ; 512 u8 itpos = 0;
1477 ; 513 u8 itmask1 = 0;
1479 ; 514 u8 itmask2 = 0;
1481 ; 515 u8 enablestatus = 0;
1483 ; 516 assert_param(IS_SPI_GET_IT_OK(SPI_IT));
1485 ; 518 itpos = (u8)((u8)1 << ((u8)SPI_IT & (u8)0x0F));
1487 00fa a40f and a,#15
1488 00fc 5f clrw x
1489 00fd 97 ld xl,a
1490 00fe a601 ld a,#1
1491 0100 5d tnzw x
1492 0101 2704 jreq L05
1493 0103 L25:
1494 0103 48 sll a
1495 0104 5a decw x
1496 0105 26fc jrne L25
1497 0107 L05:
1498 0107 6b01 ld (OFST-1,sp),a
1499 ; 521 itmask1 = (u8)((u8)SPI_IT >> (u8)4);
1501 0109 7b03 ld a,(OFST+1,sp)
1502 010b 4e swap a
1503 010c a40f and a,#15
1504 010e 6b02 ld (OFST+0,sp),a
1505 ; 523 itmask2 = (u8)((u8)1 << itmask1);
1507 0110 7b02 ld a,(OFST+0,sp)
1508 0112 5f clrw x
1509 0113 97 ld xl,a
1510 0114 a601 ld a,#1
1511 0116 5d tnzw x
1512 0117 2704 jreq L45
1513 0119 L65:
1514 0119 48 sll a
1515 011a 5a decw x
1516 011b 26fc jrne L65
1517 011d L45:
1518 011d 6b02 ld (OFST+0,sp),a
1519 ; 525 enablestatus = (u8)((u8)SPI->ICR & itmask2);
1521 011f c65202 ld a,20994
1522 0122 1402 and a,(OFST+0,sp)
1523 0124 6b02 ld (OFST+0,sp),a
1524 ; 527 if (((SPI->SR & itpos) != RESET) && enablestatus)
1526 0126 c65203 ld a,20995
1527 0129 1501 bcp a,(OFST-1,sp)
1528 012b 270a jreq L746
1530 012d 0d02 tnz (OFST+0,sp)
1531 012f 2706 jreq L746
1532 ; 530 pendingbitstatus = SET;
1534 0131 a601 ld a,#1
1535 0133 6b02 ld (OFST+0,sp),a
1537 0135 2002 jra L156
1538 0137 L746:
1539 ; 535 pendingbitstatus = RESET;
1541 0137 0f02 clr (OFST+0,sp)
1542 0139 L156:
1543 ; 538 return pendingbitstatus;
1545 0139 7b02 ld a,(OFST+0,sp)
1548 013b 5b03 addw sp,#3
1549 013d 81 ret
1592 ; 564 void SPI_ClearITPendingBit(SPI_IT_TypeDef SPI_IT)
1592 ; 565 {
1593 switch .text
1594 013e _SPI_ClearITPendingBit:
1596 013e 88 push a
1597 00000001 OFST: set 1
1600 ; 566 u8 itpos = 0;
1602 ; 567 assert_param(IS_SPI_CLEAR_IT_OK(SPI_IT));
1604 ; 572 itpos = (u8)((u8)1 << (((u8)SPI_IT & (u8)0xF0) >> 4));
1606 013f a4f0 and a,#240
1607 0141 4e swap a
1608 0142 a40f and a,#15
1609 0144 5f clrw x
1610 0145 97 ld xl,a
1611 0146 a601 ld a,#1
1612 0148 5d tnzw x
1613 0149 2704 jreq L26
1614 014b L46:
1615 014b 48 sll a
1616 014c 5a decw x
1617 014d 26fc jrne L46
1618 014f L26:
1619 014f 6b01 ld (OFST+0,sp),a
1620 ; 574 SPI->SR = (u8)(~itpos);
1622 0151 7b01 ld a,(OFST+0,sp)
1623 0153 43 cpl a
1624 0154 c75203 ld 20995,a
1625 ; 576 }
1628 0157 84 pop a
1629 0158 81 ret
1642 xdef _SPI_ClearITPendingBit
1643 xdef _SPI_GetITStatus
1644 xdef _SPI_ClearFlag
1645 xdef _SPI_GetFlagStatus
1646 xdef _SPI_BiDirectionalLineConfig
1647 xdef _SPI_GetCRCPolynomial
1648 xdef _SPI_ResetCRC
1649 xdef _SPI_GetCRC
1650 xdef _SPI_CalculateCRCCmd
1651 xdef _SPI_TransmitCRC
1652 xdef _SPI_NSSInternalSoftwareCmd
1653 xdef _SPI_ReceiveData
1654 xdef _SPI_SendData
1655 xdef _SPI_ITConfig
1656 xdef _SPI_Cmd
1657 xdef _SPI_Init_1
1658 xdef _SPI_DeInit
1677 end
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