📄 stm8s_spi.ls
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1 ; C Compiler for STM8 (COSMIC Software)
2 ; Parser V4.8.32.1 - 30 Mar 2010
3 ; Generator V4.3.4 - 23 Mar 2010
43 ; 61 void SPI_DeInit(void)
43 ; 62 {
45 switch .text
46 0000 _SPI_DeInit:
50 ; 63 SPI->CR1 = SPI_CR1_RESET_VALUE;
52 0000 725f5200 clr 20992
53 ; 64 SPI->CR2 = SPI_CR2_RESET_VALUE;
55 0004 725f5201 clr 20993
56 ; 65 SPI->ICR = SPI_ICR_RESET_VALUE;
58 0008 725f5202 clr 20994
59 ; 66 SPI->SR = SPI_SR_RESET_VALUE;
61 000c 35025203 mov 20995,#2
62 ; 67 SPI->CRCPR = SPI_CRCPR_RESET_VALUE;
64 0010 35075205 mov 20997,#7
65 ; 68 }
68 0014 81 ret
382 ; 90 void SPI_Init_1(SPI_FirstBit_TypeDef FirstBit, SPI_BaudRatePrescaler_TypeDef BaudRatePrescaler, SPI_Mode_TypeDef Mode, SPI_ClockPolarity_TypeDef ClockPolarity, SPI_ClockPhase_TypeDef ClockPhase, SPI_DataDirection_TypeDef Data_Direction, SPI_NSS_TypeDef Slave_Management, u8 CRCPolynomial)
382 ; 91 {
383 switch .text
384 0015 _SPI_Init_1:
386 0015 89 pushw x
387 00000000 OFST: set 0
390 ; 93 assert_param(IS_SPI_FIRSTBIT_OK(FirstBit));
392 ; 94 assert_param(IS_SPI_BAUDRATE_PRESCALER_OK(BaudRatePrescaler));
394 ; 95 assert_param(IS_SPI_MODE_OK(Mode));
396 ; 96 assert_param(IS_SPI_POLARITY_OK(ClockPolarity));
398 ; 97 assert_param(IS_SPI_PHASE_OK(ClockPhase));
400 ; 98 assert_param(IS_SPI_DATA_DIRECTION_OK(Data_Direction));
402 ; 99 assert_param(IS_SPI_SLAVEMANAGEMENT_OK(Slave_Management));
404 ; 100 assert_param(IS_SPI_CRC_POLYNOMIAL_OK(CRCPolynomial));
406 ; 103 SPI->CR1 = (u8)((u8)(FirstBit) |
406 ; 104 (u8)(BaudRatePrescaler) |
406 ; 105 (u8)(ClockPolarity) |
406 ; 106 (u8)(ClockPhase));
408 0016 9f ld a,xl
409 0017 1a01 or a,(OFST+1,sp)
410 0019 1a06 or a,(OFST+6,sp)
411 001b 1a07 or a,(OFST+7,sp)
412 001d c75200 ld 20992,a
413 ; 109 SPI->CR2 = (u8)((u8)(Data_Direction) | (u8)(Slave_Management));
415 0020 7b08 ld a,(OFST+8,sp)
416 0022 1a09 or a,(OFST+9,sp)
417 0024 c75201 ld 20993,a
418 ; 111 if (Mode == SPI_MODE_MASTER)
420 0027 7b05 ld a,(OFST+5,sp)
421 0029 a104 cp a,#4
422 002b 2606 jrne L102
423 ; 113 SPI->CR2 |= (u8)SPI_CR2_SSI;
425 002d 72105201 bset 20993,#0
427 0031 2004 jra L302
428 0033 L102:
429 ; 117 SPI->CR2 &= (u8)~(SPI_CR2_SSI);
431 0033 72115201 bres 20993,#0
432 0037 L302:
433 ; 121 SPI->CR1 |= (u8)(Mode);
435 0037 c65200 ld a,20992
436 003a 1a05 or a,(OFST+5,sp)
437 003c c75200 ld 20992,a
438 ; 124 SPI->CRCPR = (u8)CRCPolynomial;
440 003f 7b0a ld a,(OFST+10,sp)
441 0041 c75205 ld 20997,a
442 ; 125 }
445 0044 85 popw x
446 0045 81 ret
501 ; 143 void SPI_Cmd(FunctionalState NewState)
501 ; 144 {
502 switch .text
503 0046 _SPI_Cmd:
507 ; 146 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
509 ; 148 if (NewState != DISABLE)
511 0046 4d tnz a
512 0047 2706 jreq L332
513 ; 150 SPI->CR1 |= SPI_CR1_SPE; /* Enable the SPI peripheral*/
515 0049 721c5200 bset 20992,#6
517 004d 2004 jra L532
518 004f L332:
519 ; 154 SPI->CR1 &= (u8)(~SPI_CR1_SPE); /* Disable the SPI peripheral*/
521 004f 721d5200 bres 20992,#6
522 0053 L532:
523 ; 156 }
526 0053 81 ret
633 ; 174 void SPI_ITConfig(SPI_IT_TypeDef SPI_IT, FunctionalState NewState)
633 ; 175 {
634 switch .text
635 0054 _SPI_ITConfig:
637 0054 89 pushw x
638 0055 88 push a
639 00000001 OFST: set 1
642 ; 176 u8 itpos = 0;
644 ; 178 assert_param(IS_SPI_CONFIG_IT_OK(SPI_IT));
646 ; 179 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
648 ; 182 itpos = (u8)((u8)1 << (u8)((u8)SPI_IT & (u8)0x0F));
650 0056 9e ld a,xh
651 0057 a40f and a,#15
652 0059 5f clrw x
653 005a 97 ld xl,a
654 005b a601 ld a,#1
655 005d 5d tnzw x
656 005e 2704 jreq L41
657 0060 L61:
658 0060 48 sll a
659 0061 5a decw x
660 0062 26fc jrne L61
661 0064 L41:
662 0064 6b01 ld (OFST+0,sp),a
663 ; 184 if (NewState != DISABLE)
665 0066 0d03 tnz (OFST+2,sp)
666 0068 270a jreq L503
667 ; 186 SPI->ICR |= itpos; /* Enable interrupt*/
669 006a c65202 ld a,20994
670 006d 1a01 or a,(OFST+0,sp)
671 006f c75202 ld 20994,a
673 0072 2009 jra L703
674 0074 L503:
675 ; 190 SPI->ICR &= (u8)(~itpos); /* Disable interrupt*/
677 0074 7b01 ld a,(OFST+0,sp)
678 0076 43 cpl a
679 0077 c45202 and a,20994
680 007a c75202 ld 20994,a
681 007d L703:
682 ; 192 }
685 007d 5b03 addw sp,#3
686 007f 81 ret
718 ; 206 void SPI_SendData(u8 Data)
718 ; 207 {
719 switch .text
720 0080 _SPI_SendData:
724 ; 208 SPI->DR = Data; /* Write in the DR register the data to be sent*/
726 0080 c75204 ld 20996,a
727 ; 209 }
730 0083 81 ret
753 ; 225 u8 SPI_ReceiveData(void)
753 ; 226 {
754 switch .text
755 0084 _SPI_ReceiveData:
759 ; 227 return ((u8)SPI->DR); /* Return the data in the DR register*/
761 0084 c65204 ld a,20996
764 0087 81 ret
800 ; 246 void SPI_NSSInternalSoftwareCmd(FunctionalState NewState)
800 ; 247 {
801 switch .text
802 0088 _SPI_NSSInternalSoftwareCmd:
806 ; 249 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
808 ; 251 if (NewState != DISABLE)
810 0088 4d tnz a
811 0089 2706 jreq L353
812 ; 253 SPI->CR2 |= SPI_CR2_SSI; /* Set NSS pin internally by software*/
814 008b 72105201 bset 20993,#0
816 008f 2004 jra L553
817 0091 L353:
818 ; 257 SPI->CR2 &= (u8)(~SPI_CR2_SSI); /* Reset NSS pin internally by software*/
820 0091 72115201 bres 20993,#0
821 0095 L553:
822 ; 259 }
825 0095 81 ret
848 ; 275 void SPI_TransmitCRC(void)
848 ; 276 {
849 switch .text
850 0096 _SPI_TransmitCRC:
854 ; 277 SPI->CR2 |= SPI_CR2_CRCNEXT; /* Enable the CRC transmission*/
856 0096 72185201 bset 20993,#4
857 ; 278 }
860 009a 81 ret
897 ; 295 void SPI_CalculateCRCCmd(FunctionalState NewState)
897 ; 296 {
898 switch .text
899 009b _SPI_CalculateCRCCmd:
901 009b 88 push a
902 00000000 OFST: set 0
905 ; 298 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
907 ; 301 SPI_Cmd(DISABLE);
909 009c 4f clr a
910 009d ada7 call _SPI_Cmd
912 ; 303 if (NewState != DISABLE)
914 009f 0d01 tnz (OFST+1,sp)
915 00a1 2706 jreq L504
916 ; 305 SPI->CR2 |= SPI_CR2_CRCEN; /* Enable the CRC calculation*/
918 00a3 721a5201 bset 20993,#5
920 00a7 2004 jra L704
921 00a9 L504:
922 ; 309 SPI->CR2 &= (u8)(~SPI_CR2_CRCEN); /* Disable the CRC calculation*/
924 00a9 721b5201 bres 20993,#5
925 00ad L704:
926 ; 311 }
929 00ad 84 pop a
930 00ae 81 ret
992 ; 326 u8 SPI_GetCRC(SPI_CRC_TypeDef SPI_CRC)
992 ; 327 {
993 switch .text
994 00af _SPI_GetCRC:
996 00af 88 push a
997 00000001 OFST: set 1
1000 ; 328 u8 crcreg = 0;
1002 ; 331 assert_param(IS_SPI_CRC_OK(SPI_CRC));
1004 ; 333 if (SPI_CRC != SPI_CRC_RX)
1006 00b0 4d tnz a
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