📄 stm8s_uart3.ls
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1817 02bb L327:
1818 ; 643 else if ((UART3_FLAG == UART3_FLAG_LHDF) || (UART3_FLAG == UART3_FLAG_LSF))
1820 02bb 1e02 ldw x,(OFST+1,sp)
1821 02bd a30302 cpw x,#770
1822 02c0 2707 jreq L537
1824 02c2 1e02 ldw x,(OFST+1,sp)
1825 02c4 a30301 cpw x,#769
1826 02c7 2614 jrne L337
1827 02c9 L537:
1828 ; 645 if ((UART3->CR6 & (u8)UART3_FLAG) != (u8)0x00)
1830 02c9 c65249 ld a,21065
1831 02cc 1503 bcp a,(OFST+2,sp)
1832 02ce 2706 jreq L737
1833 ; 648 status = SET;
1835 02d0 a601 ld a,#1
1836 02d2 6b01 ld (OFST+0,sp),a
1838 02d4 2002 jra L127
1839 02d6 L737:
1840 ; 653 status = RESET;
1842 02d6 0f01 clr (OFST+0,sp)
1843 02d8 L127:
1844 ; 671 return status;
1846 02d8 7b01 ld a,(OFST+0,sp)
1849 02da 5b03 addw sp,#3
1850 02dc 81 ret
1851 02dd L337:
1852 ; 658 if ((UART3->SR & (u8)UART3_FLAG) != (u8)0x00)
1854 02dd c65240 ld a,21056
1855 02e0 1503 bcp a,(OFST+2,sp)
1856 02e2 2706 jreq L547
1857 ; 661 status = SET;
1859 02e4 a601 ld a,#1
1860 02e6 6b01 ld (OFST+0,sp),a
1862 02e8 20ee jra L127
1863 02ea L547:
1864 ; 666 status = RESET;
1866 02ea 0f01 clr (OFST+0,sp)
1867 02ec 20ea jra L127
1902 ; 708 void UART3_ClearFlag(UART3_Flag_TypeDef UART3_FLAG)
1902 ; 709 {
1903 switch .text
1904 02ee _UART3_ClearFlag:
1906 02ee 89 pushw x
1907 00000000 OFST: set 0
1910 ; 710 assert_param(IS_UART3_CLEAR_FLAG_OK(UART3_FLAG));
1912 ; 713 if (UART3_FLAG == UART3_FLAG_RXNE)
1914 02ef a30020 cpw x,#32
1915 02f2 2606 jrne L767
1916 ; 715 UART3->SR = (u8)~(UART3_SR_RXNE);
1918 02f4 35df5240 mov 21056,#223
1920 02f8 201e jra L177
1921 02fa L767:
1922 ; 718 else if (UART3_FLAG == UART3_FLAG_LBDF)
1924 02fa 1e01 ldw x,(OFST+1,sp)
1925 02fc a30210 cpw x,#528
1926 02ff 2606 jrne L377
1927 ; 720 UART3->CR4 &= (u8)(~UART3_CR4_LBDF);
1929 0301 72195247 bres 21063,#4
1931 0305 2011 jra L177
1932 0307 L377:
1933 ; 723 else if (UART3_FLAG == UART3_FLAG_LHDF)
1935 0307 1e01 ldw x,(OFST+1,sp)
1936 0309 a30302 cpw x,#770
1937 030c 2606 jrne L777
1938 ; 725 UART3->CR6 &= (u8)(~UART3_CR6_LHDF);
1940 030e 72135249 bres 21065,#1
1942 0312 2004 jra L177
1943 0314 L777:
1944 ; 730 UART3->CR6 &= (u8)(~UART3_CR6_LSF);
1946 0314 72115249 bres 21065,#0
1947 0318 L177:
1948 ; 733 }
1951 0318 85 popw x
1952 0319 81 ret
2026 ; 760 ITStatus UART3_GetITStatus(UART3_IT_TypeDef UART3_IT)
2026 ; 761 {
2027 switch .text
2028 031a _UART3_GetITStatus:
2030 031a 89 pushw x
2031 031b 89 pushw x
2032 00000002 OFST: set 2
2035 ; 762 ITStatus pendingbitstatus = RESET;
2037 ; 763 u8 itpos = 0;
2039 ; 764 u8 itmask1 = 0;
2041 ; 765 u8 itmask2 = 0;
2043 ; 766 u8 enablestatus = 0;
2045 ; 769 assert_param(IS_UART3_GET_IT_OK(UART3_IT));
2047 ; 772 itpos = (u8)((u8)1 << (u8)((u8)UART3_IT & (u8)0x0F));
2049 031c 9f ld a,xl
2050 031d a40f and a,#15
2051 031f 5f clrw x
2052 0320 97 ld xl,a
2053 0321 a601 ld a,#1
2054 0323 5d tnzw x
2055 0324 2704 jreq L65
2056 0326 L06:
2057 0326 48 sll a
2058 0327 5a decw x
2059 0328 26fc jrne L06
2060 032a L65:
2061 032a 6b01 ld (OFST-1,sp),a
2062 ; 774 itmask1 = (u8)((u8)UART3_IT >> (u8)4);
2064 032c 7b04 ld a,(OFST+2,sp)
2065 032e 4e swap a
2066 032f a40f and a,#15
2067 0331 6b02 ld (OFST+0,sp),a
2068 ; 776 itmask2 = (u8)((u8)1 << itmask1);
2070 0333 7b02 ld a,(OFST+0,sp)
2071 0335 5f clrw x
2072 0336 97 ld xl,a
2073 0337 a601 ld a,#1
2074 0339 5d tnzw x
2075 033a 2704 jreq L26
2076 033c L46:
2077 033c 48 sll a
2078 033d 5a decw x
2079 033e 26fc jrne L46
2080 0340 L26:
2081 0340 6b02 ld (OFST+0,sp),a
2082 ; 781 if (UART3_IT == UART3_IT_PE)
2084 0342 1e03 ldw x,(OFST+1,sp)
2085 0344 a30100 cpw x,#256
2086 0347 261c jrne L5301
2087 ; 784 enablestatus = (u8)((u8)UART3->CR1 & itmask2);
2089 0349 c65244 ld a,21060
2090 034c 1402 and a,(OFST+0,sp)
2091 034e 6b02 ld (OFST+0,sp),a
2092 ; 787 if (((UART3->SR & itpos) != (u8)0x00) && enablestatus)
2094 0350 c65240 ld a,21056
2095 0353 1501 bcp a,(OFST-1,sp)
2096 0355 270a jreq L7301
2098 0357 0d02 tnz (OFST+0,sp)
2099 0359 2706 jreq L7301
2100 ; 790 pendingbitstatus = SET;
2102 035b a601 ld a,#1
2103 035d 6b02 ld (OFST+0,sp),a
2105 035f 2064 jra L3401
2106 0361 L7301:
2107 ; 795 pendingbitstatus = RESET;
2109 0361 0f02 clr (OFST+0,sp)
2110 0363 2060 jra L3401
2111 0365 L5301:
2112 ; 799 else if (UART3_IT == UART3_IT_LBDF)
2114 0365 1e03 ldw x,(OFST+1,sp)
2115 0367 a30346 cpw x,#838
2116 036a 261c jrne L5401
2117 ; 802 enablestatus = (u8)((u8)UART3->CR4 & itmask2);
2119 036c c65247 ld a,21063
2120 036f 1402 and a,(OFST+0,sp)
2121 0371 6b02 ld (OFST+0,sp),a
2122 ; 804 if (((UART3->CR4 & itpos) != (u8)0x00) && enablestatus)
2124 0373 c65247 ld a,21063
2125 0376 1501 bcp a,(OFST-1,sp)
2126 0378 270a jreq L7401
2128 037a 0d02 tnz (OFST+0,sp)
2129 037c 2706 jreq L7401
2130 ; 807 pendingbitstatus = SET;
2132 037e a601 ld a,#1
2133 0380 6b02 ld (OFST+0,sp),a
2135 0382 2041 jra L3401
2136 0384 L7401:
2137 ; 812 pendingbitstatus = RESET;
2139 0384 0f02 clr (OFST+0,sp)
2140 0386 203d jra L3401
2141 0388 L5401:
2142 ; 815 else if (UART3_IT == UART3_IT_LHDF)
2144 0388 1e03 ldw x,(OFST+1,sp)
2145 038a a30412 cpw x,#1042
2146 038d 261c jrne L5501
2147 ; 818 enablestatus = (u8)((u8)UART3->CR6 & itmask2);
2149 038f c65249 ld a,21065
2150 0392 1402 and a,(OFST+0,sp)
2151 0394 6b02 ld (OFST+0,sp),a
2152 ; 820 if (((UART3->CR6 & itpos) != (u8)0x00) && enablestatus)
2154 0396 c65249 ld a,21065
2155 0399 1501 bcp a,(OFST-1,sp)
2156 039b 270a jreq L7501
2158 039d 0d02 tnz (OFST+0,sp)
2159 039f 2706 jreq L7501
2160 ; 823 pendingbitstatus = SET;
2162 03a1 a601 ld a,#1
2163 03a3 6b02 ld (OFST+0,sp),a
2165 03a5 201e jra L3401
2166 03a7 L7501:
2167 ; 828 pendingbitstatus = RESET;
2169 03a7 0f02 clr (OFST+0,sp)
2170 03a9 201a jra L3401
2171 03ab L5501:
2172 ; 834 enablestatus = (u8)((u8)UART3->CR2 & itmask2);
2174 03ab c65245 ld a,21061
2175 03ae 1402 and a,(OFST+0,sp)
2176 03b0 6b02 ld (OFST+0,sp),a
2177 ; 836 if (((UART3->SR & itpos) != (u8)0x00) && enablestatus)
2179 03b2 c65240 ld a,21056
2180 03b5 1501 bcp a,(OFST-1,sp)
2181 03b7 270a jreq L5601
2183 03b9 0d02 tnz (OFST+0,sp)
2184 03bb 2706 jreq L5601
2185 ; 839 pendingbitstatus = SET;
2187 03bd a601 ld a,#1
2188 03bf 6b02 ld (OFST+0,sp),a
2190 03c1 2002 jra L3401
2191 03c3 L5601:
2192 ; 844 pendingbitstatus = RESET;
2194 03c3 0f02 clr (OFST+0,sp)
2195 03c5 L3401:
2196 ; 848 return pendingbitstatus;
2198 03c5 7b02 ld a,(OFST+0,sp)
2201 03c7 5b04 addw sp,#4
2202 03c9 81 ret
2245 ; 884 void UART3_ClearITPendingBit(UART3_IT_TypeDef UART3_IT)
2245 ; 885 {
2246 switch .text
2247 03ca _UART3_ClearITPendingBit:
2249 03ca 89 pushw x
2250 03cb 88 push a
2251 00000001 OFST: set 1
2254 ; 886 u8 dummy = 0;
2256 03cc 0f01 clr (OFST+0,sp)
2257 ; 887 assert_param(IS_UART3_CLEAR_IT_OK(UART3_IT));
2259 ; 890 if (UART3_IT == UART3_IT_RXNE)
2261 03ce a30255 cpw x,#597
2262 03d1 2606 jrne L1111
2263 ; 892 UART3->SR = (u8)~(UART3_SR_RXNE);
2265 03d3 35df5240 mov 21056,#223
2267 03d7 2011 jra L3111
2268 03d9 L1111:
2269 ; 895 else if (UART3_IT == UART3_IT_LBDF)
2271 03d9 1e02 ldw x,(OFST+1,sp)
2272 03db a30346 cpw x,#838
2273 03de 2606 jrne L5111
2274 ; 897 UART3->CR4 &= (u8)~(UART3_CR4_LBDF);
2276 03e0 72195247 bres 21063,#4
2278 03e4 2004 jra L3111
2279 03e6 L5111:
2280 ; 902 UART3->CR6 &= (u8)(~UART3_CR6_LHDF);
2282 03e6 72135249 bres 21065,#1
2283 03ea L3111:
2284 ; 904 }
2287 03ea 5b03 addw sp,#3
2288 03ec 81 ret
2301 xref _CLK_GetClockFreq
2302 xdef _UART3_ClearITPendingBit
2303 xdef _UART3_GetITStatus
2304 xdef _UART3_ClearFlag
2305 xdef _UART3_GetFlagStatus
2306 xdef _UART3_SetAddress
2307 xdef _UART3_SendBreak
2308 xdef _UART3_SendData9
2309 xdef _UART3_SendData8
2310 xdef _UART3_ReceiveData9
2311 xdef _UART3_ReceiveData8
2312 xdef _UART3_WakeUpConfig
2313 xdef _UART3_ReceiverWakeUpCmd
2314 xdef _UART3_LINCmd
2315 xdef _UART3_LINConfig
2316 xdef _UART3_LINBreakDetectionConfig
2317 xdef _UART3_ITConfig
2318 xdef _UART3_Cmd
2319 xdef _UART3_Init
2320 xdef _UART3_DeInit
2321 xref.b c_lreg
2322 xref.b c_x
2341 xref c_lursh
2342 xref c_lsub
2343 xref c_smul
2344 xref c_ludv
2345 xref c_rtol
2346 xref c_llsh
2347 xref c_ltor
2348 end
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