📄 stm8s_uart3.ls
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1 ; C Compiler for STM8 (COSMIC Software)
2 ; Parser V4.8.32.1 - 30 Mar 2010
3 ; Generator V4.3.4 - 23 Mar 2010
52 ; 66 void UART3_DeInit(void)
52 ; 67 {
54 switch .text
55 0000 _UART3_DeInit:
57 0000 88 push a
58 00000001 OFST: set 1
61 ; 68 u8 dummy = 0;
63 ; 71 dummy = UART3->SR;
65 0001 c65240 ld a,21056
66 ; 72 dummy = UART3->DR;
68 0004 c65241 ld a,21057
69 ; 74 UART3->BRR2 = UART3_BRR2_RESET_VALUE; /*< Set UART3_BRR2 to reset value 0x00 */
71 0007 725f5243 clr 21059
72 ; 75 UART3->BRR1 = UART3_BRR1_RESET_VALUE; /*< Set UART3_BRR1 to reset value 0x00 */
74 000b 725f5242 clr 21058
75 ; 77 UART3->CR1 = UART3_CR1_RESET_VALUE; /*< Set UART3_CR1 to reset value 0x00 */
77 000f 725f5244 clr 21060
78 ; 78 UART3->CR2 = UART3_CR2_RESET_VALUE; /*< Set UART3_CR2 to reset value 0x00 */
80 0013 725f5245 clr 21061
81 ; 79 UART3->CR3 = UART3_CR3_RESET_VALUE; /*< Set UART3_CR3 to reset value 0x00 */
83 0017 725f5246 clr 21062
84 ; 80 UART3->CR4 = UART3_CR4_RESET_VALUE; /*< Set UART3_CR4 to reset value 0x00 */
86 001b 725f5247 clr 21063
87 ; 81 UART3->CR6 = UART3_CR6_RESET_VALUE; /*< Set UART3_CR6 to reset value 0x00 */
89 001f 725f5249 clr 21065
90 ; 83 }
93 0023 84 pop a
94 0024 81 ret
311 .const: section .text
312 0000 L01:
313 0000 00000064 dc.l 100
314 ; 102 void UART3_Init(u32 BaudRate, UART3_WordLength_TypeDef WordLength, UART3_StopBits_TypeDef StopBits, UART3_Parity_TypeDef Parity, UART3_Mode_TypeDef Mode)
314 ; 103 {
315 switch .text
316 0025 _UART3_Init:
318 0025 520e subw sp,#14
319 0000000e OFST: set 14
322 ; 104 u8 BRR2_1, BRR2_2 = 0;
324 ; 105 u32 BaudRate_Mantissa, BaudRate_Mantissa100 = 0;
326 ; 107 assert_param(IS_UART3_WORDLENGTH_OK(WordLength));
328 ; 109 assert_param(IS_UART3_STOPBITS_OK(StopBits));
330 ; 111 assert_param(IS_UART3_PARITY_OK(Parity));
332 ; 114 assert_param(IS_UART3_BAUDRATE_OK(BaudRate));
334 ; 117 assert_param(IS_UART3_MODE_OK((u8)Mode));
336 ; 122 UART3->CR1 &= (u8)(~UART3_CR1_M); /**< Clear the word length bit */
338 0027 72195244 bres 21060,#4
339 ; 123 UART3->CR1 |= (u8)WordLength; /**< Set the word length bit according to UART3_WordLength value */
341 002b c65244 ld a,21060
342 002e 1a15 or a,(OFST+7,sp)
343 0030 c75244 ld 21060,a
344 ; 125 UART3->CR3 &= (u8)(~UART3_CR3_STOP); /**< Clear the STOP bits */
346 0033 c65246 ld a,21062
347 0036 a4cf and a,#207
348 0038 c75246 ld 21062,a
349 ; 126 UART3->CR3 |= (u8)StopBits; /**< Set the STOP bits number according to UART3_StopBits value */
351 003b c65246 ld a,21062
352 003e 1a16 or a,(OFST+8,sp)
353 0040 c75246 ld 21062,a
354 ; 128 UART3->CR1 &= (u8)(~(UART3_CR1_PCEN | UART3_CR1_PS)); /**< Clear the Parity Control bit */
356 0043 c65244 ld a,21060
357 0046 a4f9 and a,#249
358 0048 c75244 ld 21060,a
359 ; 129 UART3->CR1 |= (u8)Parity; /**< Set the Parity Control bit to UART3_Parity value */
361 004b c65244 ld a,21060
362 004e 1a17 or a,(OFST+9,sp)
363 0050 c75244 ld 21060,a
364 ; 131 UART3->BRR1 &= (u8)(~UART3_BRR1_DIVM); /**< Clear the LSB mantissa of UART3DIV */
366 0053 725f5242 clr 21058
367 ; 132 UART3->BRR2 &= (u8)(~UART3_BRR2_DIVM); /**< Clear the MSB mantissa of UART3DIV */
369 0057 c65243 ld a,21059
370 005a a40f and a,#15
371 005c c75243 ld 21059,a
372 ; 133 UART3->BRR2 &= (u8)(~UART3_BRR2_DIVF); /**< Clear the Fraction bits of UART3DIV */
374 005f c65243 ld a,21059
375 0062 a4f0 and a,#240
376 0064 c75243 ld 21059,a
377 ; 136 BaudRate_Mantissa = ((u32)CLK_GetClockFreq() / (BaudRate << 4));
379 0067 96 ldw x,sp
380 0068 1c0011 addw x,#OFST+3
381 006b cd0000 call c_ltor
383 006e a604 ld a,#4
384 0070 cd0000 call c_llsh
386 0073 96 ldw x,sp
387 0074 1c0001 addw x,#OFST-13
388 0077 cd0000 call c_rtol
390 007a cd0000 call _CLK_GetClockFreq
392 007d 96 ldw x,sp
393 007e 1c0001 addw x,#OFST-13
394 0081 cd0000 call c_ludv
396 0084 96 ldw x,sp
397 0085 1c000b addw x,#OFST-3
398 0088 cd0000 call c_rtol
400 ; 137 BaudRate_Mantissa100 = (((u32)CLK_GetClockFreq() * 100) / (BaudRate << 4));
402 008b 96 ldw x,sp
403 008c 1c0011 addw x,#OFST+3
404 008f cd0000 call c_ltor
406 0092 a604 ld a,#4
407 0094 cd0000 call c_llsh
409 0097 96 ldw x,sp
410 0098 1c0001 addw x,#OFST-13
411 009b cd0000 call c_rtol
413 009e cd0000 call _CLK_GetClockFreq
415 00a1 a664 ld a,#100
416 00a3 cd0000 call c_smul
418 00a6 96 ldw x,sp
419 00a7 1c0001 addw x,#OFST-13
420 00aa cd0000 call c_ludv
422 00ad 96 ldw x,sp
423 00ae 1c0007 addw x,#OFST-7
424 00b1 cd0000 call c_rtol
426 ; 139 BRR2_1 = (u8)((u8)(((BaudRate_Mantissa100 - (BaudRate_Mantissa * 100))
426 ; 140 << 4) / 100) & (u8)0x0F); /**< Set the fraction of UART3DIV */
428 00b4 96 ldw x,sp
429 00b5 1c000b addw x,#OFST-3
430 00b8 cd0000 call c_ltor
432 00bb a664 ld a,#100
433 00bd cd0000 call c_smul
435 00c0 96 ldw x,sp
436 00c1 1c0001 addw x,#OFST-13
437 00c4 cd0000 call c_rtol
439 00c7 96 ldw x,sp
440 00c8 1c0007 addw x,#OFST-7
441 00cb cd0000 call c_ltor
443 00ce 96 ldw x,sp
444 00cf 1c0001 addw x,#OFST-13
445 00d2 cd0000 call c_lsub
447 00d5 a604 ld a,#4
448 00d7 cd0000 call c_llsh
450 00da ae0000 ldw x,#L01
451 00dd cd0000 call c_ludv
453 00e0 b603 ld a,c_lreg+3
454 00e2 a40f and a,#15
455 00e4 6b05 ld (OFST-9,sp),a
456 ; 141 BRR2_2 = (u8)((BaudRate_Mantissa >> 4) & (u8)0xF0);
458 00e6 96 ldw x,sp
459 00e7 1c000b addw x,#OFST-3
460 00ea cd0000 call c_ltor
462 00ed a604 ld a,#4
463 00ef cd0000 call c_lursh
465 00f2 b603 ld a,c_lreg+3
466 00f4 a4f0 and a,#240
467 00f6 b703 ld c_lreg+3,a
468 00f8 3f02 clr c_lreg+2
469 00fa 3f01 clr c_lreg+1
470 00fc 3f00 clr c_lreg
471 00fe b603 ld a,c_lreg+3
472 0100 6b06 ld (OFST-8,sp),a
473 ; 143 UART3->BRR2 = (u8)(BRR2_1 | BRR2_2);
475 0102 7b05 ld a,(OFST-9,sp)
476 0104 1a06 or a,(OFST-8,sp)
477 0106 c75243 ld 21059,a
478 ; 144 UART3->BRR1 = (u8)BaudRate_Mantissa; /**< Set the LSB mantissa of UART3DIV */
480 0109 7b0e ld a,(OFST+0,sp)
481 010b c75242 ld 21058,a
482 ; 146 if ((u8)Mode&(u8)UART3_MODE_TX_ENABLE)
484 010e 7b18 ld a,(OFST+10,sp)
485 0110 a504 bcp a,#4
486 0112 2706 jreq L141
487 ; 148 UART3->CR2 |= UART3_CR2_TEN; /**< Set the Transmitter Enable bit */
489 0114 72165245 bset 21061,#3
491 0118 2004 jra L341
492 011a L141:
493 ; 152 UART3->CR2 &= (u8)(~UART3_CR2_TEN); /**< Clear the Transmitter Disable bit */
495 011a 72175245 bres 21061,#3
496 011e L341:
497 ; 154 if ((u8)Mode & (u8)UART3_MODE_RX_ENABLE)
499 011e 7b18 ld a,(OFST+10,sp)
500 0120 a508 bcp a,#8
501 0122 2706 jreq L541
502 ; 156 UART3->CR2 |= UART3_CR2_REN; /**< Set the Receiver Enable bit */
504 0124 72145245 bset 21061,#2
506 0128 2004 jra L741
507 012a L541:
508 ; 160 UART3->CR2 &= (u8)(~UART3_CR2_REN); /**< Clear the Receiver Disable bit */
510 012a 72155245 bres 21061,#2
511 012e L741:
512 ; 162 }
515 012e 5b0e addw sp,#14
516 0130 81 ret
571 ; 182 void UART3_Cmd(FunctionalState NewState)
571 ; 183 {
572 switch .text
573 0131 _UART3_Cmd:
577 ; 185 if (NewState != DISABLE)
579 0131 4d tnz a
580 0132 2706 jreq L771
581 ; 187 UART3->CR1 &= (u8)(~UART3_CR1_UARTD); /**< UART3 Enable */
583 0134 721b5244 bres 21060,#5
585 0138 2004 jra L102
586 013a L771:
587 ; 191 UART3->CR1 |= UART3_CR1_UARTD; /**< UART3 Disable (for low power consumption) */
589 013a 721a5244 bset 21060,#5
590 013e L102:
591 ; 193 }
594 013e 81 ret
722 ; 220 void UART3_ITConfig(UART3_IT_TypeDef UART3_IT, FunctionalState NewState)
722 ; 221 {
723 switch .text
724 013f _UART3_ITConfig:
726 013f 89 pushw x
727 0140 89 pushw x
728 00000002 OFST: set 2
731 ; 222 u8 uartreg, itpos = 0x00;
733 ; 223 assert_param(IS_UART3_CONFIG_IT_OK(UART3_IT));
735 ; 224 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
737 ; 227 uartreg = (u8)(UART3_IT >> 0x08);
739 0141 9e ld a,xh
740 0142 6b01 ld (OFST-1,sp),a
741 ; 230 itpos = (u8)((u8)1 << (u8)((u8)UART3_IT & (u8)0x0F));
743 0144 9f ld a,xl
744 0145 a40f and a,#15
745 0147 5f clrw x
746 0148 97 ld xl,a
747 0149 a601 ld a,#1
748 014b 5d tnzw x
749 014c 2704 jreq L61
750 014e L02:
751 014e 48 sll a
752 014f 5a decw x
753 0150 26fc jrne L02
754 0152 L61:
755 0152 6b02 ld (OFST+0,sp),a
756 ; 232 if (NewState != DISABLE)
758 0154 0d07 tnz (OFST+5,sp)
759 0156 273a jreq L752
760 ; 235 if (uartreg == 0x01)
762 0158 7b01 ld a,(OFST-1,sp)
763 015a a101 cp a,#1
764 015c 260a jrne L162
765 ; 237 UART3->CR1 |= itpos;
767 015e c65244 ld a,21060
768 0161 1a02 or a,(OFST+0,sp)
769 0163 c75244 ld 21060,a
771 0166 2066 jra L572
772 0168 L162:
773 ; 239 else if (uartreg == 0x02)
775 0168 7b01 ld a,(OFST-1,sp)
776 016a a102 cp a,#2
777 016c 260a jrne L562
778 ; 241 UART3->CR2 |= itpos;
780 016e c65245 ld a,21061
781 0171 1a02 or a,(OFST+0,sp)
782 0173 c75245 ld 21061,a
784 0176 2056 jra L572
785 0178 L562:
786 ; 243 else if (uartreg == 0x03)
788 0178 7b01 ld a,(OFST-1,sp)
789 017a a103 cp a,#3
790 017c 260a jrne L172
791 ; 245 UART3->CR4 |= itpos;
793 017e c65247 ld a,21063
794 0181 1a02 or a,(OFST+0,sp)
795 0183 c75247 ld 21063,a
797 0186 2046 jra L572
798 0188 L172:
799 ; 249 UART3->CR6 |= itpos;
801 0188 c65249 ld a,21065
802 018b 1a02 or a,(OFST+0,sp)
803 018d c75249 ld 21065,a
804 0190 203c jra L572
805 0192 L752:
806 ; 255 if (uartreg == 0x01)
808 0192 7b01 ld a,(OFST-1,sp)
809 0194 a101 cp a,#1
810 0196 260b jrne L772
811 ; 257 UART3->CR1 &= (u8)(~itpos);
813 0198 7b02 ld a,(OFST+0,sp)
814 019a 43 cpl a
815 019b c45244 and a,21060
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