📄 stm8s_tim2.ls
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3325 03b5 c65313 ld a,21267
3326 03b8 6b02 ld (OFST-2,sp),a
3327 ; 1413 tmpccr3l = TIM2->CCR3L;
3329 03ba c65314 ld a,21268
3330 03bd 6b01 ld (OFST-3,sp),a
3331 ; 1415 tmpccr3 = (u16)(tmpccr3l);
3333 03bf 7b01 ld a,(OFST-3,sp)
3334 03c1 5f clrw x
3335 03c2 97 ld xl,a
3336 03c3 1f03 ldw (OFST-1,sp),x
3337 ; 1416 tmpccr3 |= (u16)((u16)tmpccr3h << 8);
3339 03c5 7b02 ld a,(OFST-2,sp)
3340 03c7 5f clrw x
3341 03c8 97 ld xl,a
3342 03c9 4f clr a
3343 03ca 02 rlwa x,a
3344 03cb 01 rrwa x,a
3345 03cc 1a04 or a,(OFST+0,sp)
3346 03ce 01 rrwa x,a
3347 03cf 1a03 or a,(OFST-1,sp)
3348 03d1 01 rrwa x,a
3349 03d2 1f03 ldw (OFST-1,sp),x
3350 ; 1418 return (u16)tmpccr3;
3352 03d4 1e03 ldw x,(OFST-1,sp)
3355 03d6 5b04 addw sp,#4
3356 03d8 81 ret
3379 ; 1437 u16 TIM2_GetCounter(void)
3379 ; 1438 {
3380 switch .text
3381 03d9 _TIM2_GetCounter:
3383 03d9 89 pushw x
3384 00000002 OFST: set 2
3387 ; 1440 return (u16)(((u16)TIM2->CNTRH << 8) | (u16)(TIM2->CNTRL));
3389 03da c6530b ld a,21259
3390 03dd 5f clrw x
3391 03de 97 ld xl,a
3392 03df 1f01 ldw (OFST-1,sp),x
3393 03e1 c6530a ld a,21258
3394 03e4 5f clrw x
3395 03e5 97 ld xl,a
3396 03e6 4f clr a
3397 03e7 02 rlwa x,a
3398 03e8 01 rrwa x,a
3399 03e9 1a02 or a,(OFST+0,sp)
3400 03eb 01 rrwa x,a
3401 03ec 1a01 or a,(OFST-1,sp)
3402 03ee 01 rrwa x,a
3405 03ef 5b02 addw sp,#2
3406 03f1 81 ret
3430 ; 1460 TIM2_Prescaler_TypeDef TIM2_GetPrescaler(void)
3430 ; 1461 {
3431 switch .text
3432 03f2 _TIM2_GetPrescaler:
3436 ; 1463 return (TIM2_Prescaler_TypeDef)(TIM2->PSCR);
3438 03f2 c6530c ld a,21260
3441 03f5 81 ret
3576 ; 1490 FlagStatus TIM2_GetFlagStatus(TIM2_FLAG_TypeDef TIM2_FLAG)
3576 ; 1491 {
3577 switch .text
3578 03f6 _TIM2_GetFlagStatus:
3580 03f6 5203 subw sp,#3
3581 00000003 OFST: set 3
3584 ; 1492 FlagStatus bitstatus = RESET;
3586 ; 1496 assert_param(IS_TIM2_GET_FLAG_OK(TIM2_FLAG));
3588 ; 1498 tim2_flag_l = (u8)(TIM2_FLAG);
3590 03f8 9f ld a,xl
3591 03f9 6b02 ld (OFST-1,sp),a
3592 ; 1499 tim2_flag_h = (u8)(TIM2_FLAG >> 8);
3594 03fb 9e ld a,xh
3595 03fc 6b03 ld (OFST+0,sp),a
3596 ; 1501 if (((TIM2->SR1 & tim2_flag_l) | (TIM2->SR2 & tim2_flag_h)) != (u8)RESET )
3598 03fe c65303 ld a,21251
3599 0401 1403 and a,(OFST+0,sp)
3600 0403 6b01 ld (OFST-2,sp),a
3601 0405 c65302 ld a,21250
3602 0408 1402 and a,(OFST-1,sp)
3603 040a 1a01 or a,(OFST-2,sp)
3604 040c 2706 jreq L7461
3605 ; 1503 bitstatus = SET;
3607 040e a601 ld a,#1
3608 0410 6b03 ld (OFST+0,sp),a
3610 0412 2002 jra L1561
3611 0414 L7461:
3612 ; 1507 bitstatus = RESET;
3614 0414 0f03 clr (OFST+0,sp)
3615 0416 L1561:
3616 ; 1509 return (FlagStatus)bitstatus;
3618 0416 7b03 ld a,(OFST+0,sp)
3621 0418 5b03 addw sp,#3
3622 041a 81 ret
3657 ; 1535 void TIM2_ClearFlag(TIM2_FLAG_TypeDef TIM2_FLAG)
3657 ; 1536 {
3658 switch .text
3659 041b _TIM2_ClearFlag:
3661 041b 89 pushw x
3662 00000000 OFST: set 0
3665 ; 1538 assert_param(IS_TIM2_CLEAR_FLAG_OK(TIM2_FLAG));
3667 ; 1541 TIM2->SR1 = (u8)(~((u8)(TIM2_FLAG)));
3669 041c 9f ld a,xl
3670 041d 43 cpl a
3671 041e c75302 ld 21250,a
3672 ; 1542 TIM2->SR2 = (u8)(~((u8)(TIM2_FLAG >> 8)));
3674 0421 7b01 ld a,(OFST+1,sp)
3675 0423 43 cpl a
3676 0424 c75303 ld 21251,a
3677 ; 1543 }
3680 0427 85 popw x
3681 0428 81 ret
3741 ; 1567 ITStatus TIM2_GetITStatus(TIM2_IT_TypeDef TIM2_IT)
3741 ; 1568 {
3742 switch .text
3743 0429 _TIM2_GetITStatus:
3745 0429 88 push a
3746 042a 89 pushw x
3747 00000002 OFST: set 2
3750 ; 1569 ITStatus bitstatus = RESET;
3752 ; 1571 u8 TIM2_itStatus = 0x0, TIM2_itEnable = 0x0;
3756 ; 1574 assert_param(IS_TIM2_GET_IT_OK(TIM2_IT));
3758 ; 1576 TIM2_itStatus = (u8)(TIM2->SR1 & TIM2_IT);
3760 042b c45302 and a,21250
3761 042e 6b01 ld (OFST-1,sp),a
3762 ; 1578 TIM2_itEnable = (u8)(TIM2->IER & TIM2_IT);
3764 0430 c65301 ld a,21249
3765 0433 1403 and a,(OFST+1,sp)
3766 0435 6b02 ld (OFST+0,sp),a
3767 ; 1580 if ((TIM2_itStatus != (u8)RESET ) && (TIM2_itEnable != (u8)RESET ))
3769 0437 0d01 tnz (OFST-1,sp)
3770 0439 270a jreq L7171
3772 043b 0d02 tnz (OFST+0,sp)
3773 043d 2706 jreq L7171
3774 ; 1582 bitstatus = SET;
3776 043f a601 ld a,#1
3777 0441 6b02 ld (OFST+0,sp),a
3779 0443 2002 jra L1271
3780 0445 L7171:
3781 ; 1586 bitstatus = RESET;
3783 0445 0f02 clr (OFST+0,sp)
3784 0447 L1271:
3785 ; 1588 return (ITStatus)(bitstatus);
3787 0447 7b02 ld a,(OFST+0,sp)
3790 0449 5b03 addw sp,#3
3791 044b 81 ret
3827 ; 1611 void TIM2_ClearITPendingBit(TIM2_IT_TypeDef TIM2_IT)
3827 ; 1612 {
3828 switch .text
3829 044c _TIM2_ClearITPendingBit:
3833 ; 1614 assert_param(IS_TIM2_IT_OK(TIM2_IT));
3835 ; 1617 TIM2->SR1 = (u8)(~TIM2_IT);
3837 044c 43 cpl a
3838 044d c75302 ld 21250,a
3839 ; 1618 }
3842 0450 81 ret
3888 ; 1646 static void TI1_Config(u8 TIM2_ICPolarity,
3888 ; 1647 u8 TIM2_ICSelection,
3888 ; 1648 u8 TIM2_ICFilter)
3888 ; 1649 {
3889 switch .text
3890 0451 L3_TI1_Config:
3892 0451 89 pushw x
3893 0452 88 push a
3894 00000001 OFST: set 1
3897 ; 1651 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC1E);
3899 0453 72115308 bres 21256,#0
3900 ; 1654 TIM2->CCMR1 = (u8)((TIM2->CCMR1 & (u8)(~( TIM2_CCMR_CCxS | TIM2_CCMR_ICxF ))) | (u8)(( (TIM2_ICSelection)) | ((u8)( TIM2_ICFilter << 4))));
3902 0457 7b06 ld a,(OFST+5,sp)
3903 0459 97 ld xl,a
3904 045a a610 ld a,#16
3905 045c 42 mul x,a
3906 045d 9f ld a,xl
3907 045e 1a03 or a,(OFST+2,sp)
3908 0460 6b01 ld (OFST+0,sp),a
3909 0462 c65305 ld a,21253
3910 0465 a40c and a,#12
3911 0467 1a01 or a,(OFST+0,sp)
3912 0469 c75305 ld 21253,a
3913 ; 1657 if (TIM2_ICPolarity != TIM2_ICPOLARITY_RISING)
3915 046c 0d02 tnz (OFST+1,sp)
3916 046e 2706 jreq L1671
3917 ; 1659 TIM2->CCER1 |= TIM2_CCER1_CC1P;
3919 0470 72125308 bset 21256,#1
3921 0474 2004 jra L3671
3922 0476 L1671:
3923 ; 1663 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC1P);
3925 0476 72135308 bres 21256,#1
3926 047a L3671:
3927 ; 1666 TIM2->CCER1 |= TIM2_CCER1_CC1E;
3929 047a 72105308 bset 21256,#0
3930 ; 1667 }
3933 047e 5b03 addw sp,#3
3934 0480 81 ret
3980 ; 1695 static void TI2_Config(u8 TIM2_ICPolarity,
3980 ; 1696 u8 TIM2_ICSelection,
3980 ; 1697 u8 TIM2_ICFilter)
3980 ; 1698 {
3981 switch .text
3982 0481 L5_TI2_Config:
3984 0481 89 pushw x
3985 0482 88 push a
3986 00000001 OFST: set 1
3989 ; 1700 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC2E);
3991 0483 72195308 bres 21256,#4
3992 ; 1703 TIM2->CCMR2 = (u8)((TIM2->CCMR2 & (u8)(~( TIM2_CCMR_CCxS | TIM2_CCMR_ICxF ))) | (u8)(( (TIM2_ICSelection)) | ((u8)( TIM2_ICFilter << 4))));
3994 0487 7b06 ld a,(OFST+5,sp)
3995 0489 97 ld xl,a
3996 048a a610 ld a,#16
3997 048c 42 mul x,a
3998 048d 9f ld a,xl
3999 048e 1a03 or a,(OFST+2,sp)
4000 0490 6b01 ld (OFST+0,sp),a
4001 0492 c65306 ld a,21254
4002 0495 a40c and a,#12
4003 0497 1a01 or a,(OFST+0,sp)
4004 0499 c75306 ld 21254,a
4005 ; 1707 if (TIM2_ICPolarity != TIM2_ICPOLARITY_RISING)
4007 049c 0d02 tnz (OFST+1,sp)
4008 049e 2706 jreq L5002
4009 ; 1709 TIM2->CCER1 |= TIM2_CCER1_CC2P;
4011 04a0 721a5308 bset 21256,#5
4013 04a4 2004 jra L7002
4014 04a6 L5002:
4015 ; 1713 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC2P);
4017 04a6 721b5308 bres 21256,#5
4018 04aa L7002:
4019 ; 1717 TIM2->CCER1 |= TIM2_CCER1_CC2E;
4021 04aa 72185308 bset 21256,#4
4022 ; 1719 }
4025 04ae 5b03 addw sp,#3
4026 04b0 81 ret
4072 ; 1744 static void TI3_Config(u8 TIM2_ICPolarity, u8 TIM2_ICSelection,
4072 ; 1745 u8 TIM2_ICFilter)
4072 ; 1746 {
4073 switch .text
4074 04b1 L7_TI3_Config:
4076 04b1 89 pushw x
4077 04b2 88 push a
4078 00000001 OFST: set 1
4081 ; 1748 TIM2->CCER2 &= (u8)(~TIM2_CCER2_CC3E);
4083 04b3 72115309 bres 21257,#0
4084 ; 1751 TIM2->CCMR3 = (u8)((TIM2->CCMR3 & (u8)(~( TIM2_CCMR_CCxS | TIM2_CCMR_ICxF ))) | (u8)(( (TIM2_ICSelection)) | ((u8)( TIM2_ICFilter << 4))));
4086 04b7 7b06 ld a,(OFST+5,sp)
4087 04b9 97 ld xl,a
4088 04ba a610 ld a,#16
4089 04bc 42 mul x,a
4090 04bd 9f ld a,xl
4091 04be 1a03 or a,(OFST+2,sp)
4092 04c0 6b01 ld (OFST+0,sp),a
4093 04c2 c65307 ld a,21255
4094 04c5 a40c and a,#12
4095 04c7 1a01 or a,(OFST+0,sp)
4096 04c9 c75307 ld 21255,a
4097 ; 1755 if (TIM2_ICPolarity != TIM2_ICPOLARITY_RISING)
4099 04cc 0d02 tnz (OFST+1,sp)
4100 04ce 2706 jreq L1302
4101 ; 1757 TIM2->CCER2 |= TIM2_CCER2_CC3P;
4103 04d0 72125309 bset 21257,#1
4105 04d4 2004 jra L3302
4106 04d6 L1302:
4107 ; 1761 TIM2->CCER2 &= (u8)(~TIM2_CCER2_CC3P);
4109 04d6 72135309 bres 21257,#1
4110 04da L3302:
4111 ; 1764 TIM2->CCER2 |= TIM2_CCER2_CC3E;
4113 04da 72105309 bset 21257,#0
4114 ; 1765 }
4117 04de 5b03 addw sp,#3
4118 04e0 81 ret
4131 xdef _TIM2_ClearITPendingBit
4132 xdef _TIM2_GetITStatus
4133 xdef _TIM2_ClearFlag
4134 xdef _TIM2_GetFlagStatus
4135 xdef _TIM2_GetPrescaler
4136 xdef _TIM2_GetCounter
4137 xdef _TIM2_GetCapture3
4138 xdef _TIM2_GetCapture2
4139 xdef _TIM2_GetCapture1
4140 xdef _TIM2_SetIC3Prescaler
4141 xdef _TIM2_SetIC2Prescaler
4142 xdef _TIM2_SetIC1Prescaler
4143 xdef _TIM2_SetCompare3
4144 xdef _TIM2_SetCompare2
4145 xdef _TIM2_SetCompare1
4146 xdef _TIM2_SetAutoreload
4147 xdef _TIM2_SetCounter
4148 xdef _TIM2_SelectOCxM
4149 xdef _TIM2_CCxCmd
4150 xdef _TIM2_OC3PolarityConfig
4151 xdef _TIM2_OC2PolarityConfig
4152 xdef _TIM2_OC1PolarityConfig
4153 xdef _TIM2_GenerateEvent
4154 xdef _TIM2_OC3PreloadConfig
4155 xdef _TIM2_OC2PreloadConfig
4156 xdef _TIM2_OC1PreloadConfig
4157 xdef _TIM2_ARRPreloadConfig
4158 xdef _TIM2_ForcedOC3Config
4159 xdef _TIM2_ForcedOC2Config
4160 xdef _TIM2_ForcedOC1Config
4161 xdef _TIM2_PrescalerConfig
4162 xdef _TIM2_SelectOnePulseMode
4163 xdef _TIM2_UpdateRequestConfig
4164 xdef _TIM2_UpdateDisableConfig
4165 xdef _TIM2_ITConfig
4166 xdef _TIM2_Cmd
4167 xdef _TIM2_PWMIConfig
4168 xdef _TIM2_ICInit
4169 xdef _TIM2_OC3Init
4170 xdef _TIM2_OC2Init
4171 xdef _TIM2_OC1Init
4172 xdef _TIM2_TimeBaseInit
4173 xdef _TIM2_DeInit
4192 end
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