📄 stm8s_tim2.ls
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1157 ; 401 TI1_Config(TIM2_ICPolarity, TIM2_ICSelection,
1157 ; 402 TIM2_ICFilter);
1159 0169 7b09 ld a,(OFST+7,sp)
1160 016b 88 push a
1161 016c 7b08 ld a,(OFST+6,sp)
1162 016e 97 ld xl,a
1163 016f 7b05 ld a,(OFST+3,sp)
1164 0171 95 ld xh,a
1165 0172 cd0451 call L3_TI1_Config
1167 0175 84 pop a
1168 ; 405 TIM2_SetIC1Prescaler(TIM2_ICPrescaler);
1170 0176 7b08 ld a,(OFST+6,sp)
1171 0178 cd0340 call _TIM2_SetIC1Prescaler
1173 ; 408 TI2_Config(icpolarity, icselection, TIM2_ICFilter);
1175 017b 7b09 ld a,(OFST+7,sp)
1176 017d 88 push a
1177 017e 7b03 ld a,(OFST+1,sp)
1178 0180 97 ld xl,a
1179 0181 7b02 ld a,(OFST+0,sp)
1180 0183 95 ld xh,a
1181 0184 cd0481 call L5_TI2_Config
1183 0187 84 pop a
1184 ; 411 TIM2_SetIC2Prescaler(TIM2_ICPrescaler);
1186 0188 7b08 ld a,(OFST+6,sp)
1187 018a cd034d call _TIM2_SetIC2Prescaler
1190 018d 2024 jra L154
1191 018f L744:
1192 ; 416 TI2_Config(TIM2_ICPolarity, TIM2_ICSelection,
1192 ; 417 TIM2_ICFilter);
1194 018f 7b09 ld a,(OFST+7,sp)
1195 0191 88 push a
1196 0192 7b08 ld a,(OFST+6,sp)
1197 0194 97 ld xl,a
1198 0195 7b05 ld a,(OFST+3,sp)
1199 0197 95 ld xh,a
1200 0198 cd0481 call L5_TI2_Config
1202 019b 84 pop a
1203 ; 420 TIM2_SetIC2Prescaler(TIM2_ICPrescaler);
1205 019c 7b08 ld a,(OFST+6,sp)
1206 019e cd034d call _TIM2_SetIC2Prescaler
1208 ; 423 TI1_Config(icpolarity, icselection, TIM2_ICFilter);
1210 01a1 7b09 ld a,(OFST+7,sp)
1211 01a3 88 push a
1212 01a4 7b03 ld a,(OFST+1,sp)
1213 01a6 97 ld xl,a
1214 01a7 7b02 ld a,(OFST+0,sp)
1215 01a9 95 ld xh,a
1216 01aa cd0451 call L3_TI1_Config
1218 01ad 84 pop a
1219 ; 426 TIM2_SetIC1Prescaler(TIM2_ICPrescaler);
1221 01ae 7b08 ld a,(OFST+6,sp)
1222 01b0 cd0340 call _TIM2_SetIC1Prescaler
1224 01b3 L154:
1225 ; 428 }
1228 01b3 5b04 addw sp,#4
1229 01b5 81 ret
1284 ; 446 void TIM2_Cmd(FunctionalState NewState)
1284 ; 447 {
1285 switch .text
1286 01b6 _TIM2_Cmd:
1290 ; 449 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1292 ; 452 if (NewState != DISABLE)
1294 01b6 4d tnz a
1295 01b7 2706 jreq L105
1296 ; 454 TIM2->CR1 |= TIM2_CR1_CEN;
1298 01b9 72105300 bset 21248,#0
1300 01bd 2004 jra L305
1301 01bf L105:
1302 ; 458 TIM2->CR1 &= (u8)(~TIM2_CR1_CEN);
1304 01bf 72115300 bres 21248,#0
1305 01c3 L305:
1306 ; 460 }
1309 01c3 81 ret
1388 ; 485 void TIM2_ITConfig(TIM2_IT_TypeDef TIM2_IT, FunctionalState NewState)
1388 ; 486 {
1389 switch .text
1390 01c4 _TIM2_ITConfig:
1392 01c4 89 pushw x
1393 00000000 OFST: set 0
1396 ; 488 assert_param(IS_TIM2_IT_OK(TIM2_IT));
1398 ; 489 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1400 ; 491 if (NewState != DISABLE)
1402 01c5 9f ld a,xl
1403 01c6 4d tnz a
1404 01c7 2709 jreq L345
1405 ; 494 TIM2->IER |= TIM2_IT;
1407 01c9 9e ld a,xh
1408 01ca ca5301 or a,21249
1409 01cd c75301 ld 21249,a
1411 01d0 2009 jra L545
1412 01d2 L345:
1413 ; 499 TIM2->IER &= (u8)(~TIM2_IT);
1415 01d2 7b01 ld a,(OFST+1,sp)
1416 01d4 43 cpl a
1417 01d5 c45301 and a,21249
1418 01d8 c75301 ld 21249,a
1419 01db L545:
1420 ; 501 }
1423 01db 85 popw x
1424 01dc 81 ret
1460 ; 519 void TIM2_UpdateDisableConfig(FunctionalState NewState)
1460 ; 520 {
1461 switch .text
1462 01dd _TIM2_UpdateDisableConfig:
1466 ; 522 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1468 ; 525 if (NewState != DISABLE)
1470 01dd 4d tnz a
1471 01de 2706 jreq L565
1472 ; 527 TIM2->CR1 |= TIM2_CR1_UDIS;
1474 01e0 72125300 bset 21248,#1
1476 01e4 2004 jra L765
1477 01e6 L565:
1478 ; 531 TIM2->CR1 &= (u8)(~TIM2_CR1_UDIS);
1480 01e6 72135300 bres 21248,#1
1481 01ea L765:
1482 ; 533 }
1485 01ea 81 ret
1543 ; 552 void TIM2_UpdateRequestConfig(TIM2_UpdateSource_TypeDef TIM2_UpdateSource)
1543 ; 553 {
1544 switch .text
1545 01eb _TIM2_UpdateRequestConfig:
1549 ; 555 assert_param(IS_TIM2_UPDATE_SOURCE_OK(TIM2_UpdateSource));
1551 ; 558 if (TIM2_UpdateSource != TIM2_UPDATESOURCE_GLOBAL)
1553 01eb 4d tnz a
1554 01ec 2706 jreq L716
1555 ; 560 TIM2->CR1 |= TIM2_CR1_URS;
1557 01ee 72145300 bset 21248,#2
1559 01f2 2004 jra L126
1560 01f4 L716:
1561 ; 564 TIM2->CR1 &= (u8)(~TIM2_CR1_URS);
1563 01f4 72155300 bres 21248,#2
1564 01f8 L126:
1565 ; 566 }
1568 01f8 81 ret
1625 ; 586 void TIM2_SelectOnePulseMode(TIM2_OPMode_TypeDef TIM2_OPMode)
1625 ; 587 {
1626 switch .text
1627 01f9 _TIM2_SelectOnePulseMode:
1631 ; 589 assert_param(IS_TIM2_OPM_MODE_OK(TIM2_OPMode));
1633 ; 592 if (TIM2_OPMode != TIM2_OPMODE_REPETITIVE)
1635 01f9 4d tnz a
1636 01fa 2706 jreq L156
1637 ; 594 TIM2->CR1 |= TIM2_CR1_OPM;
1639 01fc 72165300 bset 21248,#3
1641 0200 2004 jra L356
1642 0202 L156:
1643 ; 598 TIM2->CR1 &= (u8)(~TIM2_CR1_OPM);
1645 0202 72175300 bres 21248,#3
1646 0206 L356:
1647 ; 601 }
1650 0206 81 ret
1718 ; 641 void TIM2_PrescalerConfig(TIM2_Prescaler_TypeDef Prescaler,
1718 ; 642 TIM2_PSCReloadMode_TypeDef TIM2_PSCReloadMode)
1718 ; 643 {
1719 switch .text
1720 0207 _TIM2_PrescalerConfig:
1724 ; 645 assert_param(IS_TIM2_PRESCALER_RELOAD_OK(TIM2_PSCReloadMode));
1726 ; 646 assert_param(IS_TIM2_PRESCALER_OK(Prescaler));
1728 ; 649 TIM2->PSCR = Prescaler;
1730 0207 9e ld a,xh
1731 0208 c7530c ld 21260,a
1732 ; 652 TIM2->EGR = TIM2_PSCReloadMode;
1734 020b 9f ld a,xl
1735 020c c75304 ld 21252,a
1736 ; 653 }
1739 020f 81 ret
1797 ; 673 void TIM2_ForcedOC1Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
1797 ; 674 {
1798 switch .text
1799 0210 _TIM2_ForcedOC1Config:
1801 0210 88 push a
1802 00000000 OFST: set 0
1805 ; 676 assert_param(IS_TIM2_FORCED_ACTION_OK(TIM2_ForcedAction));
1807 ; 679 TIM2->CCMR1 = (u8)((TIM2->CCMR1 & (u8)(~TIM2_CCMR_OCM)) | (u8)TIM2_ForcedAction);
1809 0211 c65305 ld a,21253
1810 0214 a48f and a,#143
1811 0216 1a01 or a,(OFST+1,sp)
1812 0218 c75305 ld 21253,a
1813 ; 680 }
1816 021b 84 pop a
1817 021c 81 ret
1853 ; 700 void TIM2_ForcedOC2Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
1853 ; 701 {
1854 switch .text
1855 021d _TIM2_ForcedOC2Config:
1857 021d 88 push a
1858 00000000 OFST: set 0
1861 ; 703 assert_param(IS_TIM2_FORCED_ACTION_OK(TIM2_ForcedAction));
1863 ; 706 TIM2->CCMR2 = (u8)((TIM2->CCMR2 & (u8)(~TIM2_CCMR_OCM)) | (u8)TIM2_ForcedAction);
1865 021e c65306 ld a,21254
1866 0221 a48f and a,#143
1867 0223 1a01 or a,(OFST+1,sp)
1868 0225 c75306 ld 21254,a
1869 ; 707 }
1872 0228 84 pop a
1873 0229 81 ret
1909 ; 727 void TIM2_ForcedOC3Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
1909 ; 728 {
1910 switch .text
1911 022a _TIM2_ForcedOC3Config:
1913 022a 88 push a
1914 00000000 OFST: set 0
1917 ; 730 assert_param(IS_TIM2_FORCED_ACTION_OK(TIM2_ForcedAction));
1919 ; 733 TIM2->CCMR3 = (u8)((TIM2->CCMR3 & (u8)(~TIM2_CCMR_OCM)) | (u8)TIM2_ForcedAction);
1921 022b c65307 ld a,21255
1922 022e a48f and a,#143
1923 0230 1a01 or a,(OFST+1,sp)
1924 0232 c75307 ld 21255,a
1925 ; 734 }
1928 0235 84 pop a
1929 0236 81 ret
1965 ; 752 void TIM2_ARRPreloadConfig(FunctionalState NewState)
1965 ; 753 {
1966 switch .text
1967 0237 _TIM2_ARRPreloadConfig:
1971 ; 755 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1973 ; 758 if (NewState != DISABLE)
1975 0237 4d tnz a
1976 0238 2706 jreq L7001
1977 ; 760 TIM2->CR1 |= TIM2_CR1_ARPE;
1979 023a 721e5300 bset 21248,#7
1981 023e 2004 jra L1101
1982 0240 L7001:
1983 ; 764 TIM2->CR1 &= (u8)(~TIM2_CR1_ARPE);
1985 0240 721f5300 bres 21248,#7
1986 0244 L1101:
1987 ; 766 }
1990 0244 81 ret
2026 ; 784 void TIM2_OC1PreloadConfig(FunctionalState NewState)
2026 ; 785 {
2027 switch .text
2028 0245 _TIM2_OC1PreloadConfig:
2032 ; 787 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2034 ; 790 if (NewState != DISABLE)
2036 0245 4d tnz a
2037 0246 2706 jreq L1301
2038 ; 792 TIM2->CCMR1 |= TIM2_CCMR_OCxPE;
2040 0248 72165305 bset 21253,#3
2042 024c 2004 jra L3301
2043 024e L1301:
2044 ; 796 TIM2->CCMR1 &= (u8)(~TIM2_CCMR_OCxPE);
2046 024e 72175305 bres 21253,#3
2047 0252 L3301:
2048 ; 798 }
2051 0252 81 ret
2087 ; 816 void TIM2_OC2PreloadConfig(FunctionalState NewState)
2087 ; 817 {
2088 switch .text
2089 0253 _TIM2_OC2PreloadConfig:
2093 ; 819 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2095 ; 822 if (NewState != DISABLE)
2097 0253 4d tnz a
2098 0254 2706 jreq L3501
2099 ; 824 TIM2->CCMR2 |= TIM2_CCMR_OCxPE;
2101 0256 72165306 bset 21254,#3
2103 025a 2004 jra L5501
2104 025c L3501:
2105 ; 828 TIM2->CCMR2 &= (u8)(~TIM2_CCMR_OCxPE);
2107 025c 72175306 bres 21254,#3
2108 0260 L5501:
2109 ; 830 }
2112 0260 81 ret
2148 ; 848 void TIM2_OC3PreloadConfig(FunctionalState NewState)
2148 ; 849 {
2149 switch .text
2150 0261 _TIM2_OC3PreloadConfig:
2154 ; 851 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2156 ; 854 if (NewState != DISABLE)
2158 0261 4d tnz a
2159 0262 2706 jreq L5701
2160 ; 856 TIM2->CCMR3 |= TIM2_CCMR_OCxPE;
2162 0264 72165307 bset 21255,#3
2164 0268 2004 jra L7701
2165 026a L5701:
2166 ; 860 TIM2->CCMR3 &= (u8)(~TIM2_CCMR_OCxPE);
2168 026a 72175307 bres 21255,#3
2169 026e L7701:
2170 ; 862 }
2173 026e 81 ret
2246 ; 884 void TIM2_GenerateEvent(TIM2_EventSource_TypeDef TIM2_EventSource)
2246 ; 885 {
2247 switch .text
2248 026f _TIM2_GenerateEvent:
2252 ; 887 assert_param(IS_TIM2_EVENT_SOURCE_OK(TIM2_EventSource));
2254 ; 890 TIM2->EGR = TIM2_EventSource;
2256 026f c75304 ld 21252,a
2257 ; 891 }
2260 0272 81 ret
2296 ; 911 void TIM2_OC1PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
2296 ; 912 {
2297 switch .text
2298 0273 _TIM2_OC1PolarityConfig:
2302 ; 914 assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
2304 ; 917 if (TIM2_OCPolarity != TIM2_OCPOLARITY_HIGH)
2306 0273 4d tnz a
2307 0274 2706 jreq L1511
2308 ; 919 TIM2->CCER1 |= TIM2_CCER1_CC1P;
2310 0276 72125308 bset 21256,#1
2312 027a 2004 jra L3511
2313 027c L1511:
2314 ; 923 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC1P);
2316 027c 72135308 bres 21256,#1
2317 0280 L3511:
2318 ; 925 }
2321 0280 81 ret
2357 ; 945 void TIM2_OC2PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
2357 ; 946 {
2358 switch .text
2359 0281 _TIM2_OC2PolarityConfig:
2363 ; 948 assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
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