📄 stm8s_uart2.ls
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2255 ; 819 FlagStatus status = RESET;
2257 ; 822 assert_param(IS_UART2_FLAG_OK(UART2_FLAG));
2259 ; 825 if (UART2_FLAG == UART2_FLAG_LBDF)
2261 0302 a30210 cpw x,#528
2262 0305 2610 jrne L3211
2263 ; 827 if ((UART2->CR4 & (u8)UART2_FLAG) != (u8)0x00)
2265 0307 9f ld a,xl
2266 0308 c45247 and a,21063
2267 030b 2706 jreq L5211
2268 ; 830 status = SET;
2270 030d a601 ld a,#1
2271 030f 6b01 ld (OFST+0,sp),a
2273 0311 2039 jra L1311
2274 0313 L5211:
2275 ; 835 status = RESET;
2277 0313 0f01 clr (OFST+0,sp)
2278 0315 2035 jra L1311
2279 0317 L3211:
2280 ; 838 else if (UART2_FLAG == UART2_FLAG_SBK)
2282 0317 1e02 ldw x,(OFST+1,sp)
2283 0319 a30101 cpw x,#257
2284 031c 2611 jrne L3311
2285 ; 840 if ((UART2->CR2 & (u8)UART2_FLAG) != (u8)0x00)
2287 031e c65245 ld a,21061
2288 0321 1503 bcp a,(OFST+2,sp)
2289 0323 2706 jreq L5311
2290 ; 843 status = SET;
2292 0325 a601 ld a,#1
2293 0327 6b01 ld (OFST+0,sp),a
2295 0329 2021 jra L1311
2296 032b L5311:
2297 ; 848 status = RESET;
2299 032b 0f01 clr (OFST+0,sp)
2300 032d 201d jra L1311
2301 032f L3311:
2302 ; 851 else if ((UART2_FLAG == UART2_FLAG_LHDF) || (UART2_FLAG == UART2_FLAG_LSF))
2304 032f 1e02 ldw x,(OFST+1,sp)
2305 0331 a30302 cpw x,#770
2306 0334 2707 jreq L5411
2308 0336 1e02 ldw x,(OFST+1,sp)
2309 0338 a30301 cpw x,#769
2310 033b 2614 jrne L3411
2311 033d L5411:
2312 ; 853 if ((UART2->CR6 & (u8)UART2_FLAG) != (u8)0x00)
2314 033d c65249 ld a,21065
2315 0340 1503 bcp a,(OFST+2,sp)
2316 0342 2706 jreq L7411
2317 ; 856 status = SET;
2319 0344 a601 ld a,#1
2320 0346 6b01 ld (OFST+0,sp),a
2322 0348 2002 jra L1311
2323 034a L7411:
2324 ; 861 status = RESET;
2326 034a 0f01 clr (OFST+0,sp)
2327 034c L1311:
2328 ; 879 return status;
2330 034c 7b01 ld a,(OFST+0,sp)
2333 034e 5b03 addw sp,#3
2334 0350 81 ret
2335 0351 L3411:
2336 ; 866 if ((UART2->SR & (u8)UART2_FLAG) != (u8)0x00)
2338 0351 c65240 ld a,21056
2339 0354 1503 bcp a,(OFST+2,sp)
2340 0356 2706 jreq L5511
2341 ; 869 status = SET;
2343 0358 a601 ld a,#1
2344 035a 6b01 ld (OFST+0,sp),a
2346 035c 20ee jra L1311
2347 035e L5511:
2348 ; 874 status = RESET;
2350 035e 0f01 clr (OFST+0,sp)
2351 0360 20ea jra L1311
2386 ; 916 void UART2_ClearFlag(UART2_Flag_TypeDef UART2_FLAG)
2386 ; 917 {
2387 switch .text
2388 0362 _UART2_ClearFlag:
2390 0362 89 pushw x
2391 00000000 OFST: set 0
2394 ; 918 assert_param(IS_UART2_CLEAR_FLAG_OK(UART2_FLAG));
2396 ; 921 if (UART2_FLAG == UART2_FLAG_RXNE)
2398 0363 a30020 cpw x,#32
2399 0366 2606 jrne L7711
2400 ; 923 UART2->SR = (u8)~(UART2_SR_RXNE);
2402 0368 35df5240 mov 21056,#223
2404 036c 201e jra L1021
2405 036e L7711:
2406 ; 926 else if (UART2_FLAG == UART2_FLAG_LBDF)
2408 036e 1e01 ldw x,(OFST+1,sp)
2409 0370 a30210 cpw x,#528
2410 0373 2606 jrne L3021
2411 ; 928 UART2->CR4 &= (u8)(~UART2_CR4_LBDF);
2413 0375 72195247 bres 21063,#4
2415 0379 2011 jra L1021
2416 037b L3021:
2417 ; 931 else if (UART2_FLAG == UART2_FLAG_LHDF)
2419 037b 1e01 ldw x,(OFST+1,sp)
2420 037d a30302 cpw x,#770
2421 0380 2606 jrne L7021
2422 ; 933 UART2->CR6 &= (u8)(~UART2_CR6_LHDF);
2424 0382 72135249 bres 21065,#1
2426 0386 2004 jra L1021
2427 0388 L7021:
2428 ; 938 UART2->CR6 &= (u8)(~UART2_CR6_LSF);
2430 0388 72115249 bres 21065,#0
2431 038c L1021:
2432 ; 941 }
2435 038c 85 popw x
2436 038d 81 ret
2510 ; 968 ITStatus UART2_GetITStatus(UART2_IT_TypeDef UART2_IT)
2510 ; 969 {
2511 switch .text
2512 038e _UART2_GetITStatus:
2514 038e 89 pushw x
2515 038f 89 pushw x
2516 00000002 OFST: set 2
2519 ; 970 ITStatus pendingbitstatus = RESET;
2521 ; 971 u8 itpos = 0;
2523 ; 972 u8 itmask1 = 0;
2525 ; 973 u8 itmask2 = 0;
2527 ; 974 u8 enablestatus = 0;
2529 ; 977 assert_param(IS_UART2_GET_IT_OK(UART2_IT));
2531 ; 980 itpos = (u8)((u8)1 << (u8)((u8)UART2_IT & (u8)0x0F));
2533 0390 9f ld a,xl
2534 0391 a40f and a,#15
2535 0393 5f clrw x
2536 0394 97 ld xl,a
2537 0395 a601 ld a,#1
2538 0397 5d tnzw x
2539 0398 2704 jreq L27
2540 039a L47:
2541 039a 48 sll a
2542 039b 5a decw x
2543 039c 26fc jrne L47
2544 039e L27:
2545 039e 6b01 ld (OFST-1,sp),a
2546 ; 982 itmask1 = (u8)((u8)UART2_IT >> (u8)4);
2548 03a0 7b04 ld a,(OFST+2,sp)
2549 03a2 4e swap a
2550 03a3 a40f and a,#15
2551 03a5 6b02 ld (OFST+0,sp),a
2552 ; 984 itmask2 = (u8)((u8)1 << itmask1);
2554 03a7 7b02 ld a,(OFST+0,sp)
2555 03a9 5f clrw x
2556 03aa 97 ld xl,a
2557 03ab a601 ld a,#1
2558 03ad 5d tnzw x
2559 03ae 2704 jreq L67
2560 03b0 L001:
2561 03b0 48 sll a
2562 03b1 5a decw x
2563 03b2 26fc jrne L001
2564 03b4 L67:
2565 03b4 6b02 ld (OFST+0,sp),a
2566 ; 989 if (UART2_IT == UART2_IT_PE)
2568 03b6 1e03 ldw x,(OFST+1,sp)
2569 03b8 a30100 cpw x,#256
2570 03bb 261c jrne L5421
2571 ; 992 enablestatus = (u8)((u8)UART2->CR1 & itmask2);
2573 03bd c65244 ld a,21060
2574 03c0 1402 and a,(OFST+0,sp)
2575 03c2 6b02 ld (OFST+0,sp),a
2576 ; 995 if (((UART2->SR & itpos) != (u8)0x00) && enablestatus)
2578 03c4 c65240 ld a,21056
2579 03c7 1501 bcp a,(OFST-1,sp)
2580 03c9 270a jreq L7421
2582 03cb 0d02 tnz (OFST+0,sp)
2583 03cd 2706 jreq L7421
2584 ; 998 pendingbitstatus = SET;
2586 03cf a601 ld a,#1
2587 03d1 6b02 ld (OFST+0,sp),a
2589 03d3 2064 jra L3521
2590 03d5 L7421:
2591 ; 1003 pendingbitstatus = RESET;
2593 03d5 0f02 clr (OFST+0,sp)
2594 03d7 2060 jra L3521
2595 03d9 L5421:
2596 ; 1007 else if (UART2_IT == UART2_IT_LBDF)
2598 03d9 1e03 ldw x,(OFST+1,sp)
2599 03db a30346 cpw x,#838
2600 03de 261c jrne L5521
2601 ; 1010 enablestatus = (u8)((u8)UART2->CR4 & itmask2);
2603 03e0 c65247 ld a,21063
2604 03e3 1402 and a,(OFST+0,sp)
2605 03e5 6b02 ld (OFST+0,sp),a
2606 ; 1012 if (((UART2->CR4 & itpos) != (u8)0x00) && enablestatus)
2608 03e7 c65247 ld a,21063
2609 03ea 1501 bcp a,(OFST-1,sp)
2610 03ec 270a jreq L7521
2612 03ee 0d02 tnz (OFST+0,sp)
2613 03f0 2706 jreq L7521
2614 ; 1015 pendingbitstatus = SET;
2616 03f2 a601 ld a,#1
2617 03f4 6b02 ld (OFST+0,sp),a
2619 03f6 2041 jra L3521
2620 03f8 L7521:
2621 ; 1020 pendingbitstatus = RESET;
2623 03f8 0f02 clr (OFST+0,sp)
2624 03fa 203d jra L3521
2625 03fc L5521:
2626 ; 1023 else if (UART2_IT == UART2_IT_LHDF)
2628 03fc 1e03 ldw x,(OFST+1,sp)
2629 03fe a30412 cpw x,#1042
2630 0401 261c jrne L5621
2631 ; 1026 enablestatus = (u8)((u8)UART2->CR6 & itmask2);
2633 0403 c65249 ld a,21065
2634 0406 1402 and a,(OFST+0,sp)
2635 0408 6b02 ld (OFST+0,sp),a
2636 ; 1028 if (((UART2->CR6 & itpos) != (u8)0x00) && enablestatus)
2638 040a c65249 ld a,21065
2639 040d 1501 bcp a,(OFST-1,sp)
2640 040f 270a jreq L7621
2642 0411 0d02 tnz (OFST+0,sp)
2643 0413 2706 jreq L7621
2644 ; 1031 pendingbitstatus = SET;
2646 0415 a601 ld a,#1
2647 0417 6b02 ld (OFST+0,sp),a
2649 0419 201e jra L3521
2650 041b L7621:
2651 ; 1036 pendingbitstatus = RESET;
2653 041b 0f02 clr (OFST+0,sp)
2654 041d 201a jra L3521
2655 041f L5621:
2656 ; 1042 enablestatus = (u8)((u8)UART2->CR2 & itmask2);
2658 041f c65245 ld a,21061
2659 0422 1402 and a,(OFST+0,sp)
2660 0424 6b02 ld (OFST+0,sp),a
2661 ; 1044 if (((UART2->SR & itpos) != (u8)0x00) && enablestatus)
2663 0426 c65240 ld a,21056
2664 0429 1501 bcp a,(OFST-1,sp)
2665 042b 270a jreq L5721
2667 042d 0d02 tnz (OFST+0,sp)
2668 042f 2706 jreq L5721
2669 ; 1047 pendingbitstatus = SET;
2671 0431 a601 ld a,#1
2672 0433 6b02 ld (OFST+0,sp),a
2674 0435 2002 jra L3521
2675 0437 L5721:
2676 ; 1052 pendingbitstatus = RESET;
2678 0437 0f02 clr (OFST+0,sp)
2679 0439 L3521:
2680 ; 1056 return pendingbitstatus;
2682 0439 7b02 ld a,(OFST+0,sp)
2685 043b 5b04 addw sp,#4
2686 043d 81 ret
2729 ; 1092 void UART2_ClearITPendingBit(UART2_IT_TypeDef UART2_IT)
2729 ; 1093 {
2730 switch .text
2731 043e _UART2_ClearITPendingBit:
2733 043e 89 pushw x
2734 043f 88 push a
2735 00000001 OFST: set 1
2738 ; 1094 u8 dummy = 0;
2740 0440 0f01 clr (OFST+0,sp)
2741 ; 1095 assert_param(IS_UART2_CLEAR_IT_OK(UART2_IT));
2743 ; 1098 if (UART2_IT == UART2_IT_RXNE)
2745 0442 a30255 cpw x,#597
2746 0445 2606 jrne L1231
2747 ; 1100 UART2->SR = (u8)~(UART2_SR_RXNE);
2749 0447 35df5240 mov 21056,#223
2751 044b 2011 jra L3231
2752 044d L1231:
2753 ; 1103 else if (UART2_IT == UART2_IT_LBDF)
2755 044d 1e02 ldw x,(OFST+1,sp)
2756 044f a30346 cpw x,#838
2757 0452 2606 jrne L5231
2758 ; 1105 UART2->CR4 &= (u8)~(UART2_CR4_LBDF);
2760 0454 72195247 bres 21063,#4
2762 0458 2004 jra L3231
2763 045a L5231:
2764 ; 1110 UART2->CR6 &= (u8)(~UART2_CR6_LHDF);
2766 045a 72135249 bres 21065,#1
2767 045e L3231:
2768 ; 1112 }
2771 045e 5b03 addw sp,#3
2772 0460 81 ret
2785 xref _CLK_GetClockFreq
2786 xdef _UART2_ClearITPendingBit
2787 xdef _UART2_GetITStatus
2788 xdef _UART2_ClearFlag
2789 xdef _UART2_GetFlagStatus
2790 xdef _UART2_SetPrescaler
2791 xdef _UART2_SetGuardTime
2792 xdef _UART2_SetAddress
2793 xdef _UART2_SendBreak
2794 xdef _UART2_SendData9
2795 xdef _UART2_SendData8
2796 xdef _UART2_ReceiveData9
2797 xdef _UART2_ReceiveData8
2798 xdef _UART2_ReceiverWakeUpCmd
2799 xdef _UART2_WakeUpConfig
2800 xdef _UART2_SmartCardNACKCmd
2801 xdef _UART2_SmartCardCmd
2802 xdef _UART2_LINCmd
2803 xdef _UART2_LINConfig
2804 xdef _UART2_LINBreakDetectionConfig
2805 xdef _UART2_IrDACmd
2806 xdef _UART2_IrDAConfig
2807 xdef _UART2_ITConfig
2808 xdef _UART2_Cmd
2809 xdef _UART2_Init
2810 xdef _UART2_DeInit
2811 xref.b c_lreg
2812 xref.b c_x
2831 xref c_lursh
2832 xref c_lsub
2833 xref c_smul
2834 xref c_ludv
2835 xref c_rtol
2836 xref c_llsh
2837 xref c_ltor
2838 end
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