📄 stm8s_uart2.ls
字号:
962 01e0 c45245 and a,21061
963 01e3 c75245 ld 21061,a
965 01e6 201a jra L533
966 01e8 L343:
967 ; 279 else if (uartreg == 0x03)
969 01e8 7b01 ld a,(OFST-1,sp)
970 01ea a103 cp a,#3
971 01ec 260b jrne L743
972 ; 281 UART2->CR4 &= (u8)(~itpos);
974 01ee 7b02 ld a,(OFST+0,sp)
975 01f0 43 cpl a
976 01f1 c45247 and a,21063
977 01f4 c75247 ld 21063,a
979 01f7 2009 jra L533
980 01f9 L743:
981 ; 285 UART2->CR6 &= (u8)(~itpos);
983 01f9 7b02 ld a,(OFST+0,sp)
984 01fb 43 cpl a
985 01fc c45249 and a,21065
986 01ff c75249 ld 21065,a
987 0202 L533:
988 ; 288 }
991 0202 5b04 addw sp,#4
992 0204 81 ret
1049 ; 306 void UART2_IrDAConfig(UART2_IrDAMode_TypeDef UART2_IrDAMode)
1049 ; 307 {
1050 switch .text
1051 0205 _UART2_IrDAConfig:
1055 ; 308 assert_param(IS_UART2_IRDAMODE_OK(UART2_IrDAMode));
1057 ; 310 if (UART2_IrDAMode != UART2_IRDAMODE_NORMAL)
1059 0205 4d tnz a
1060 0206 2706 jreq L104
1061 ; 312 UART2->CR5 |= UART2_CR5_IRLP;
1063 0208 72145248 bset 21064,#2
1065 020c 2004 jra L304
1066 020e L104:
1067 ; 316 UART2->CR5 &= ((u8)~UART2_CR5_IRLP);
1069 020e 72155248 bres 21064,#2
1070 0212 L304:
1071 ; 318 }
1074 0212 81 ret
1109 ; 337 void UART2_IrDACmd(FunctionalState NewState)
1109 ; 338 {
1110 switch .text
1111 0213 _UART2_IrDACmd:
1115 ; 341 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1117 ; 343 if (NewState != DISABLE)
1119 0213 4d tnz a
1120 0214 2706 jreq L324
1121 ; 346 UART2->CR5 |= UART2_CR5_IREN;
1123 0216 72125248 bset 21064,#1
1125 021a 2004 jra L524
1126 021c L324:
1127 ; 351 UART2->CR5 &= ((u8)~UART2_CR5_IREN);
1129 021c 72135248 bres 21064,#1
1130 0220 L524:
1131 ; 353 }
1134 0220 81 ret
1193 ; 371 void UART2_LINBreakDetectionConfig(UART2_LINBreakDetectionLength_TypeDef UART2_LINBreakDetectionLength)
1193 ; 372 {
1194 switch .text
1195 0221 _UART2_LINBreakDetectionConfig:
1199 ; 373 assert_param(IS_UART2_LINBREAKDETECTIONLENGTH_OK(UART2_LINBreakDetectionLength));
1201 ; 375 if (UART2_LINBreakDetectionLength != UART2_LINBREAKDETECTIONLENGTH_10BITS)
1203 0221 4d tnz a
1204 0222 2706 jreq L554
1205 ; 377 UART2->CR4 |= UART2_CR4_LBDL;
1207 0224 721a5247 bset 21063,#5
1209 0228 2004 jra L754
1210 022a L554:
1211 ; 381 UART2->CR4 &= ((u8)~UART2_CR4_LBDL);
1213 022a 721b5247 bres 21063,#5
1214 022e L754:
1215 ; 383 }
1218 022e 81 ret
1339 ; 405 void UART2_LINConfig(UART2_LinMode_TypeDef UART2_Mode, UART2_LinAutosync_TypeDef UART2_Autosync, UART2_LinDivUp_TypeDef UART2_DivUp)
1339 ; 406 {
1340 switch .text
1341 022f _UART2_LINConfig:
1343 022f 89 pushw x
1344 00000000 OFST: set 0
1347 ; 407 assert_param(IS_UART2_SLAVE_OK(UART2_Mode));
1349 ; 409 assert_param(IS_UART2_AUTOSYNC_OK(UART2_Autosync));
1351 ; 411 assert_param(IS_UART2_DIVUP_OK(UART2_DivUp));
1353 ; 413 if (UART2_Mode != UART2_LIN_MODE_MASTER)
1355 0230 9e ld a,xh
1356 0231 4d tnz a
1357 0232 2706 jreq L735
1358 ; 415 UART2->CR6 |= UART2_CR6_LSLV;
1360 0234 721a5249 bset 21065,#5
1362 0238 2004 jra L145
1363 023a L735:
1364 ; 419 UART2->CR6 &= ((u8)~UART2_CR6_LSLV);
1366 023a 721b5249 bres 21065,#5
1367 023e L145:
1368 ; 422 if (UART2_Autosync != UART2_LIN_AUTOSYNC_DISABLE)
1370 023e 0d02 tnz (OFST+2,sp)
1371 0240 2706 jreq L345
1372 ; 424 UART2->CR6 |= UART2_CR6_LASE ;
1374 0242 72185249 bset 21065,#4
1376 0246 2004 jra L545
1377 0248 L345:
1378 ; 428 UART2->CR6 &= ((u8)~ UART2_CR6_LASE );
1380 0248 72195249 bres 21065,#4
1381 024c L545:
1382 ; 431 if (UART2_DivUp != UART2_LIN_DIVUP_LBRR1)
1384 024c 0d05 tnz (OFST+5,sp)
1385 024e 2706 jreq L745
1386 ; 433 UART2->CR6 |= UART2_CR6_LDUM;
1388 0250 721e5249 bset 21065,#7
1390 0254 2004 jra L155
1391 0256 L745:
1392 ; 437 UART2->CR6 &= ((u8)~ UART2_CR6_LDUM);
1394 0256 721f5249 bres 21065,#7
1395 025a L155:
1396 ; 440 }
1399 025a 85 popw x
1400 025b 81 ret
1435 ; 460 void UART2_LINCmd(FunctionalState NewState)
1435 ; 461 {
1436 switch .text
1437 025c _UART2_LINCmd:
1441 ; 462 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1443 ; 464 if (NewState != DISABLE)
1445 025c 4d tnz a
1446 025d 2706 jreq L175
1447 ; 467 UART2->CR3 |= UART2_CR3_LINEN;
1449 025f 721c5246 bset 21062,#6
1451 0263 2004 jra L375
1452 0265 L175:
1453 ; 472 UART2->CR3 &= ((u8)~UART2_CR3_LINEN);
1455 0265 721d5246 bres 21062,#6
1456 0269 L375:
1457 ; 474 }
1460 0269 81 ret
1495 ; 493 void UART2_SmartCardCmd(FunctionalState NewState)
1495 ; 494 {
1496 switch .text
1497 026a _UART2_SmartCardCmd:
1501 ; 495 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1503 ; 497 if (NewState != DISABLE)
1505 026a 4d tnz a
1506 026b 2706 jreq L316
1507 ; 500 UART2->CR5 |= UART2_CR5_SCEN;
1509 026d 721a5248 bset 21064,#5
1511 0271 2004 jra L516
1512 0273 L316:
1513 ; 505 UART2->CR5 &= ((u8)(~UART2_CR5_SCEN));
1515 0273 721b5248 bres 21064,#5
1516 0277 L516:
1517 ; 507 }
1520 0277 81 ret
1556 ; 527 void UART2_SmartCardNACKCmd(FunctionalState NewState)
1556 ; 528 {
1557 switch .text
1558 0278 _UART2_SmartCardNACKCmd:
1562 ; 529 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1564 ; 531 if (NewState != DISABLE)
1566 0278 4d tnz a
1567 0279 2706 jreq L536
1568 ; 534 UART2->CR5 |= UART2_CR5_NACK;
1570 027b 72185248 bset 21064,#4
1572 027f 2004 jra L736
1573 0281 L536:
1574 ; 539 UART2->CR5 &= ((u8)~(UART2_CR5_NACK));
1576 0281 72195248 bres 21064,#4
1577 0285 L736:
1578 ; 541 }
1581 0285 81 ret
1638 ; 559 void UART2_WakeUpConfig(UART2_WakeUp_TypeDef UART2_WakeUp)
1638 ; 560 {
1639 switch .text
1640 0286 _UART2_WakeUpConfig:
1644 ; 561 assert_param(IS_UART2_WAKEUP_OK(UART2_WakeUp));
1646 ; 563 UART2->CR1 &= ((u8)~UART2_CR1_WAKE);
1648 0286 72175244 bres 21060,#3
1649 ; 564 UART2->CR1 |= (u8)UART2_WakeUp;
1651 028a ca5244 or a,21060
1652 028d c75244 ld 21060,a
1653 ; 565 }
1656 0290 81 ret
1692 ; 585 void UART2_ReceiverWakeUpCmd(FunctionalState NewState)
1692 ; 586 {
1693 switch .text
1694 0291 _UART2_ReceiverWakeUpCmd:
1698 ; 587 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1700 ; 589 if (NewState != DISABLE)
1702 0291 4d tnz a
1703 0292 2706 jreq L507
1704 ; 592 UART2->CR2 |= UART2_CR2_RWU;
1706 0294 72125245 bset 21061,#1
1708 0298 2004 jra L707
1709 029a L507:
1710 ; 597 UART2->CR2 &= ((u8)~UART2_CR2_RWU);
1712 029a 72135245 bres 21061,#1
1713 029e L707:
1714 ; 599 }
1717 029e 81 ret
1740 ; 617 u8 UART2_ReceiveData8(void)
1740 ; 618 {
1741 switch .text
1742 029f _UART2_ReceiveData8:
1746 ; 619 return ((u8)UART2->DR);
1748 029f c65241 ld a,21057
1751 02a2 81 ret
1774 ; 637 u16 UART2_ReceiveData9(void)
1774 ; 638 {
1775 switch .text
1776 02a3 _UART2_ReceiveData9:
1778 02a3 89 pushw x
1779 00000002 OFST: set 2
1782 ; 639 return (u16)((((u16)UART2->DR) | ((u16)(((u16)((u16)UART2->CR1 & (u16)UART2_CR1_R8)) << 1))) & ((u16)0x01FF));
1784 02a4 c65244 ld a,21060
1785 02a7 5f clrw x
1786 02a8 a480 and a,#128
1787 02aa 5f clrw x
1788 02ab 02 rlwa x,a
1789 02ac 58 sllw x
1790 02ad 1f01 ldw (OFST-1,sp),x
1791 02af c65241 ld a,21057
1792 02b2 5f clrw x
1793 02b3 97 ld xl,a
1794 02b4 01 rrwa x,a
1795 02b5 1a02 or a,(OFST+0,sp)
1796 02b7 01 rrwa x,a
1797 02b8 1a01 or a,(OFST-1,sp)
1798 02ba 01 rrwa x,a
1799 02bb 01 rrwa x,a
1800 02bc a4ff and a,#255
1801 02be 01 rrwa x,a
1802 02bf a401 and a,#1
1803 02c1 01 rrwa x,a
1806 02c2 5b02 addw sp,#2
1807 02c4 81 ret
1839 ; 661 void UART2_SendData8(u8 Data)
1839 ; 662 {
1840 switch .text
1841 02c5 _UART2_SendData8:
1845 ; 664 UART2->DR = Data;
1847 02c5 c75241 ld 21057,a
1848 ; 665 }
1851 02c8 81 ret
1883 ; 684 void UART2_SendData9(u16 Data)
1883 ; 685 {
1884 switch .text
1885 02c9 _UART2_SendData9:
1887 02c9 89 pushw x
1888 00000000 OFST: set 0
1891 ; 686 UART2->CR1 &= ((u8)~UART2_CR1_T8); /**< Clear the transmit data bit 8 */
1893 02ca 721d5244 bres 21060,#6
1894 ; 687 UART2->CR1 |= (u8)(((u8)(Data >> 2)) & UART2_CR1_T8); /**< Write the transmit data bit [8] */
1896 02ce 54 srlw x
1897 02cf 54 srlw x
1898 02d0 9f ld a,xl
1899 02d1 a440 and a,#64
1900 02d3 ca5244 or a,21060
1901 02d6 c75244 ld 21060,a
1902 ; 688 UART2->DR = (u8)(Data); /**< Write the transmit data bit [0:7] */
1904 02d9 7b02 ld a,(OFST+2,sp)
1905 02db c75241 ld 21057,a
1906 ; 690 }
1909 02de 85 popw x
1910 02df 81 ret
1933 ; 705 void UART2_SendBreak(void)
1933 ; 706 {
1934 switch .text
1935 02e0 _UART2_SendBreak:
1939 ; 707 UART2->CR2 |= UART2_CR2_SBK;
1941 02e0 72105245 bset 21061,#0
1942 ; 708 }
1945 02e4 81 ret
1977 ; 727 void UART2_SetAddress(u8 UART2_Address)
1977 ; 728 {
1978 switch .text
1979 02e5 _UART2_SetAddress:
1981 02e5 88 push a
1982 00000000 OFST: set 0
1985 ; 730 assert_param(IS_UART2_ADDRESS_OK(UART2_Address));
1987 ; 733 UART2->CR4 &= ((u8)~UART2_CR4_ADD);
1989 02e6 c65247 ld a,21063
1990 02e9 a4f0 and a,#240
1991 02eb c75247 ld 21063,a
1992 ; 735 UART2->CR4 |= UART2_Address;
1994 02ee c65247 ld a,21063
1995 02f1 1a01 or a,(OFST+1,sp)
1996 02f3 c75247 ld 21063,a
1997 ; 736 }
2000 02f6 84 pop a
2001 02f7 81 ret
2033 ; 754 void UART2_SetGuardTime(u8 UART2_GuardTime)
2033 ; 755 {
2034 switch .text
2035 02f8 _UART2_SetGuardTime:
2039 ; 757 UART2->GTR = UART2_GuardTime;
2041 02f8 c7524a ld 21066,a
2042 ; 758 }
2045 02fb 81 ret
2077 ; 792 void UART2_SetPrescaler(u8 UART2_Prescaler)
2077 ; 793 {
2078 switch .text
2079 02fc _UART2_SetPrescaler:
2083 ; 795 UART2->PSCR = UART2_Prescaler;
2085 02fc c7524b ld 21067,a
2086 ; 796 }
2089 02ff 81 ret
2246 ; 817 FlagStatus UART2_GetFlagStatus(UART2_Flag_TypeDef UART2_FLAG)
2246 ; 818 {
2247 switch .text
2248 0300 _UART2_GetFlagStatus:
2250 0300 89 pushw x
2251 0301 88 push a
2252 00000001 OFST: set 1
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