📄 stm8s_uart2.ls
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1 ; C Compiler for STM8 (COSMIC Software)
2 ; Parser V4.8.32.1 - 30 Mar 2010
3 ; Generator V4.3.4 - 23 Mar 2010
52 ; 65 void UART2_DeInit(void)
52 ; 66 {
54 switch .text
55 0000 _UART2_DeInit:
57 0000 88 push a
58 00000001 OFST: set 1
61 ; 67 u8 dummy = 0;
63 ; 70 dummy = UART2->SR;
65 0001 c65240 ld a,21056
66 ; 71 dummy = UART2->DR;
68 0004 c65241 ld a,21057
69 ; 73 UART2->BRR2 = UART2_BRR2_RESET_VALUE; /*< Set UART2_BRR2 to reset value 0x00 */
71 0007 725f5243 clr 21059
72 ; 74 UART2->BRR1 = UART2_BRR1_RESET_VALUE; /*< Set UART2_BRR1 to reset value 0x00 */
74 000b 725f5242 clr 21058
75 ; 76 UART2->CR1 = UART2_CR1_RESET_VALUE; /*< Set UART2_CR1 to reset value 0x00 */
77 000f 725f5244 clr 21060
78 ; 77 UART2->CR2 = UART2_CR2_RESET_VALUE; /*< Set UART2_CR2 to reset value 0x00 */
80 0013 725f5245 clr 21061
81 ; 78 UART2->CR3 = UART2_CR3_RESET_VALUE; /*< Set UART2_CR3 to reset value 0x00 */
83 0017 725f5246 clr 21062
84 ; 79 UART2->CR4 = UART2_CR4_RESET_VALUE; /*< Set UART2_CR4 to reset value 0x00 */
86 001b 725f5247 clr 21063
87 ; 80 UART2->CR5 = UART2_CR5_RESET_VALUE; /*< Set UART2_CR5 to reset value 0x00 */
89 001f 725f5248 clr 21064
90 ; 81 UART2->CR6 = UART2_CR6_RESET_VALUE; /*< Set UART2_CR6 to reset value 0x00 */
92 0023 725f5249 clr 21065
93 ; 83 }
96 0027 84 pop a
97 0028 81 ret
408 .const: section .text
409 0000 L01:
410 0000 00000064 dc.l 100
411 ; 103 void UART2_Init(u32 BaudRate, UART2_WordLength_TypeDef WordLength, UART2_StopBits_TypeDef StopBits, UART2_Parity_TypeDef Parity, UART2_SyncMode_TypeDef SyncMode, UART2_Mode_TypeDef Mode)
411 ; 104 {
412 switch .text
413 0029 _UART2_Init:
415 0029 520e subw sp,#14
416 0000000e OFST: set 14
419 ; 105 u8 BRR2_1, BRR2_2 = 0;
421 ; 106 u32 BaudRate_Mantissa, BaudRate_Mantissa100 = 0;
423 ; 109 assert_param(IS_UART2_BAUDRATE_OK(BaudRate));
425 ; 111 assert_param(IS_UART2_WORDLENGTH_OK(WordLength));
427 ; 113 assert_param(IS_UART2_STOPBITS_OK(StopBits));
429 ; 115 assert_param(IS_UART2_PARITY_OK(Parity));
431 ; 118 assert_param(IS_UART2_MODE_OK((u8)Mode));
433 ; 122 assert_param(IS_UART2_SYNCMODE_OK((u8)SyncMode));
435 ; 124 UART2->CR1 &= (u8)(~UART2_CR1_M); /**< Clear the word length bit */
437 002b 72195244 bres 21060,#4
438 ; 125 UART2->CR1 |= (u8)WordLength; /**< Set the word length bit according to UART2_WordLength value */
440 002f c65244 ld a,21060
441 0032 1a15 or a,(OFST+7,sp)
442 0034 c75244 ld 21060,a
443 ; 127 UART2->CR3 &= (u8)(~UART2_CR3_STOP); /**< Clear the STOP bits */
445 0037 c65246 ld a,21062
446 003a a4cf and a,#207
447 003c c75246 ld 21062,a
448 ; 128 UART2->CR3 |= (u8)StopBits; /**< Set the STOP bits number according to UART2_StopBits value */
450 003f c65246 ld a,21062
451 0042 1a16 or a,(OFST+8,sp)
452 0044 c75246 ld 21062,a
453 ; 130 UART2->CR1 &= (u8)(~(UART2_CR1_PCEN | UART2_CR1_PS )); /**< Clear the Parity Control bit */
455 0047 c65244 ld a,21060
456 004a a4f9 and a,#249
457 004c c75244 ld 21060,a
458 ; 131 UART2->CR1 |= (u8)Parity; /**< Set the Parity Control bit to UART2_Parity value */
460 004f c65244 ld a,21060
461 0052 1a17 or a,(OFST+9,sp)
462 0054 c75244 ld 21060,a
463 ; 133 UART2->BRR1 &= (u8)(~UART2_BRR1_DIVM); /**< Clear the LSB mantissa of UARTDIV */
465 0057 725f5242 clr 21058
466 ; 134 UART2->BRR2 &= (u8)(~UART2_BRR2_DIVM); /**< Clear the MSB mantissa of UARTDIV */
468 005b c65243 ld a,21059
469 005e a40f and a,#15
470 0060 c75243 ld 21059,a
471 ; 135 UART2->BRR2 &= (u8)(~UART2_BRR2_DIVF); /**< Clear the Fraction bits of UARTDIV */
473 0063 c65243 ld a,21059
474 0066 a4f0 and a,#240
475 0068 c75243 ld 21059,a
476 ; 138 BaudRate_Mantissa = ((u32)CLK_GetClockFreq() / (BaudRate << 4));
478 006b 96 ldw x,sp
479 006c 1c0011 addw x,#OFST+3
480 006f cd0000 call c_ltor
482 0072 a604 ld a,#4
483 0074 cd0000 call c_llsh
485 0077 96 ldw x,sp
486 0078 1c0001 addw x,#OFST-13
487 007b cd0000 call c_rtol
489 007e cd0000 call _CLK_GetClockFreq
491 0081 96 ldw x,sp
492 0082 1c0001 addw x,#OFST-13
493 0085 cd0000 call c_ludv
495 0088 96 ldw x,sp
496 0089 1c000b addw x,#OFST-3
497 008c cd0000 call c_rtol
499 ; 139 BaudRate_Mantissa100 = (((u32)CLK_GetClockFreq() * 100) / (BaudRate << 4));
501 008f 96 ldw x,sp
502 0090 1c0011 addw x,#OFST+3
503 0093 cd0000 call c_ltor
505 0096 a604 ld a,#4
506 0098 cd0000 call c_llsh
508 009b 96 ldw x,sp
509 009c 1c0001 addw x,#OFST-13
510 009f cd0000 call c_rtol
512 00a2 cd0000 call _CLK_GetClockFreq
514 00a5 a664 ld a,#100
515 00a7 cd0000 call c_smul
517 00aa 96 ldw x,sp
518 00ab 1c0001 addw x,#OFST-13
519 00ae cd0000 call c_ludv
521 00b1 96 ldw x,sp
522 00b2 1c0007 addw x,#OFST-7
523 00b5 cd0000 call c_rtol
525 ; 141 BRR2_1 = (u8)((u8)(((BaudRate_Mantissa100 - (BaudRate_Mantissa * 100))
525 ; 142 << 4) / 100) & (u8)0x0F); /**< Set the fraction of UARTDIV */
527 00b8 96 ldw x,sp
528 00b9 1c000b addw x,#OFST-3
529 00bc cd0000 call c_ltor
531 00bf a664 ld a,#100
532 00c1 cd0000 call c_smul
534 00c4 96 ldw x,sp
535 00c5 1c0001 addw x,#OFST-13
536 00c8 cd0000 call c_rtol
538 00cb 96 ldw x,sp
539 00cc 1c0007 addw x,#OFST-7
540 00cf cd0000 call c_ltor
542 00d2 96 ldw x,sp
543 00d3 1c0001 addw x,#OFST-13
544 00d6 cd0000 call c_lsub
546 00d9 a604 ld a,#4
547 00db cd0000 call c_llsh
549 00de ae0000 ldw x,#L01
550 00e1 cd0000 call c_ludv
552 00e4 b603 ld a,c_lreg+3
553 00e6 a40f and a,#15
554 00e8 6b05 ld (OFST-9,sp),a
555 ; 143 BRR2_2 = (u8)((BaudRate_Mantissa >> 4) & (u8)0xF0);
557 00ea 96 ldw x,sp
558 00eb 1c000b addw x,#OFST-3
559 00ee cd0000 call c_ltor
561 00f1 a604 ld a,#4
562 00f3 cd0000 call c_lursh
564 00f6 b603 ld a,c_lreg+3
565 00f8 a4f0 and a,#240
566 00fa b703 ld c_lreg+3,a
567 00fc 3f02 clr c_lreg+2
568 00fe 3f01 clr c_lreg+1
569 0100 3f00 clr c_lreg
570 0102 b603 ld a,c_lreg+3
571 0104 6b06 ld (OFST-8,sp),a
572 ; 145 UART2->BRR2 = (u8)(BRR2_1 | BRR2_2);
574 0106 7b05 ld a,(OFST-9,sp)
575 0108 1a06 or a,(OFST-8,sp)
576 010a c75243 ld 21059,a
577 ; 146 UART2->BRR1 = (u8)BaudRate_Mantissa; /**< Set the LSB mantissa of UARTDIV */
579 010d 7b0e ld a,(OFST+0,sp)
580 010f c75242 ld 21058,a
581 ; 148 UART2->CR2 &= (u8)~(UART2_CR2_TEN | UART2_CR2_REN); /**< Disable the Transmitter and Receiver before seting the LBCL, CPOL and CPHA bits */
583 0112 c65245 ld a,21061
584 0115 a4f3 and a,#243
585 0117 c75245 ld 21061,a
586 ; 149 UART2->CR3 &= (u8)~(UART2_CR3_CPOL | UART2_CR3_CPHA | UART2_CR3_LBCL); /**< Clear the Clock Polarity, lock Phase, Last Bit Clock pulse */
588 011a c65246 ld a,21062
589 011d a4f8 and a,#248
590 011f c75246 ld 21062,a
591 ; 150 UART2->CR3 |= (u8)((u8)SyncMode & (u8)(UART2_CR3_CPOL | UART2_CR3_CPHA | UART2_CR3_LBCL)); /**< Set the Clock Polarity, lock Phase, Last Bit Clock pulse */
593 0122 7b18 ld a,(OFST+10,sp)
594 0124 a407 and a,#7
595 0126 ca5246 or a,21062
596 0129 c75246 ld 21062,a
597 ; 152 if ((u8)Mode & (u8)UART2_MODE_TX_ENABLE)
599 012c 7b19 ld a,(OFST+11,sp)
600 012e a504 bcp a,#4
601 0130 2706 jreq L571
602 ; 154 UART2->CR2 |= (u8)UART2_CR2_TEN; /**< Set the Transmitter Enable bit */
604 0132 72165245 bset 21061,#3
606 0136 2004 jra L771
607 0138 L571:
608 ; 158 UART2->CR2 &= (u8)(~UART2_CR2_TEN); /**< Clear the Transmitter Disable bit */
610 0138 72175245 bres 21061,#3
611 013c L771:
612 ; 160 if ((u8)Mode & (u8)UART2_MODE_RX_ENABLE)
614 013c 7b19 ld a,(OFST+11,sp)
615 013e a508 bcp a,#8
616 0140 2706 jreq L102
617 ; 162 UART2->CR2 |= (u8)UART2_CR2_REN; /**< Set the Receiver Enable bit */
619 0142 72145245 bset 21061,#2
621 0146 2004 jra L302
622 0148 L102:
623 ; 166 UART2->CR2 &= (u8)(~UART2_CR2_REN); /**< Clear the Receiver Disable bit */
625 0148 72155245 bres 21061,#2
626 014c L302:
627 ; 169 if ((u8)SyncMode&(u8)UART2_SYNCMODE_CLOCK_DISABLE)
629 014c 7b18 ld a,(OFST+10,sp)
630 014e a580 bcp a,#128
631 0150 2706 jreq L502
632 ; 171 UART2->CR3 &= (u8)(~UART2_CR3_CKEN); /**< Clear the Clock Enable bit */
634 0152 72175246 bres 21062,#3
636 0156 200a jra L702
637 0158 L502:
638 ; 176 UART2->CR3 |= (u8)((u8)SyncMode & UART2_CR3_CKEN);
640 0158 7b18 ld a,(OFST+10,sp)
641 015a a408 and a,#8
642 015c ca5246 or a,21062
643 015f c75246 ld 21062,a
644 0162 L702:
645 ; 178 }
648 0162 5b0e addw sp,#14
649 0164 81 ret
704 ; 198 void UART2_Cmd(FunctionalState NewState)
704 ; 199 {
705 switch .text
706 0165 _UART2_Cmd:
710 ; 201 if (NewState != DISABLE)
712 0165 4d tnz a
713 0166 2706 jreq L732
714 ; 203 UART2->CR1 &= (u8)(~UART2_CR1_UARTD); /**< UART2 Enable */
716 0168 721b5244 bres 21060,#5
718 016c 2004 jra L142
719 016e L732:
720 ; 207 UART2->CR1 |= UART2_CR1_UARTD; /**< UART2 Disable (for low power consumption) */
722 016e 721a5244 bset 21060,#5
723 0172 L142:
724 ; 209 }
727 0172 81 ret
855 ; 236 void UART2_ITConfig(UART2_IT_TypeDef UART2_IT, FunctionalState NewState)
855 ; 237 {
856 switch .text
857 0173 _UART2_ITConfig:
859 0173 89 pushw x
860 0174 89 pushw x
861 00000002 OFST: set 2
864 ; 238 u8 uartreg, itpos = 0x00;
866 ; 239 assert_param(IS_UART2_CONFIG_IT_OK(UART2_IT));
868 ; 240 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
870 ; 243 uartreg = (u8)(UART2_IT >> 0x08);
872 0175 9e ld a,xh
873 0176 6b01 ld (OFST-1,sp),a
874 ; 246 itpos = (u8)((u8)1 << (u8)((u8)UART2_IT & (u8)0x0F));
876 0178 9f ld a,xl
877 0179 a40f and a,#15
878 017b 5f clrw x
879 017c 97 ld xl,a
880 017d a601 ld a,#1
881 017f 5d tnzw x
882 0180 2704 jreq L61
883 0182 L02:
884 0182 48 sll a
885 0183 5a decw x
886 0184 26fc jrne L02
887 0186 L61:
888 0186 6b02 ld (OFST+0,sp),a
889 ; 248 if (NewState != DISABLE)
891 0188 0d07 tnz (OFST+5,sp)
892 018a 273a jreq L713
893 ; 251 if (uartreg == 0x01)
895 018c 7b01 ld a,(OFST-1,sp)
896 018e a101 cp a,#1
897 0190 260a jrne L123
898 ; 253 UART2->CR1 |= itpos;
900 0192 c65244 ld a,21060
901 0195 1a02 or a,(OFST+0,sp)
902 0197 c75244 ld 21060,a
904 019a 2066 jra L533
905 019c L123:
906 ; 255 else if (uartreg == 0x02)
908 019c 7b01 ld a,(OFST-1,sp)
909 019e a102 cp a,#2
910 01a0 260a jrne L523
911 ; 257 UART2->CR2 |= itpos;
913 01a2 c65245 ld a,21061
914 01a5 1a02 or a,(OFST+0,sp)
915 01a7 c75245 ld 21061,a
917 01aa 2056 jra L533
918 01ac L523:
919 ; 259 else if (uartreg == 0x03)
921 01ac 7b01 ld a,(OFST-1,sp)
922 01ae a103 cp a,#3
923 01b0 260a jrne L133
924 ; 261 UART2->CR4 |= itpos;
926 01b2 c65247 ld a,21063
927 01b5 1a02 or a,(OFST+0,sp)
928 01b7 c75247 ld 21063,a
930 01ba 2046 jra L533
931 01bc L133:
932 ; 265 UART2->CR6 |= itpos;
934 01bc c65249 ld a,21065
935 01bf 1a02 or a,(OFST+0,sp)
936 01c1 c75249 ld 21065,a
937 01c4 203c jra L533
938 01c6 L713:
939 ; 271 if (uartreg == 0x01)
941 01c6 7b01 ld a,(OFST-1,sp)
942 01c8 a101 cp a,#1
943 01ca 260b jrne L733
944 ; 273 UART2->CR1 &= (u8)(~itpos);
946 01cc 7b02 ld a,(OFST+0,sp)
947 01ce 43 cpl a
948 01cf c45244 and a,21060
949 01d2 c75244 ld 21060,a
951 01d5 202b jra L533
952 01d7 L733:
953 ; 275 else if (uartreg == 0x02)
955 01d7 7b01 ld a,(OFST-1,sp)
956 01d9 a102 cp a,#2
957 01db 260b jrne L343
958 ; 277 UART2->CR2 &= (u8)(~itpos);
960 01dd 7b02 ld a,(OFST+0,sp)
961 01df 43 cpl a
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